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4 | 4 | #ifndef __SDW_REGISTERS_H
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5 | 5 | #define __SDW_REGISTERS_H
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6 | 6 |
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| 7 | +#include <linux/bitfield.h> |
| 8 | +#include <linux/bits.h> |
| 9 | + |
7 | 10 | /*
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8 | 11 | * SDW registers as defined by MIPI 1.2 Spec
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9 | 12 | */
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329 | 332 | * 2:0 Control Number[2:0]
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330 | 333 | */
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331 | 334 |
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332 |
| -#define SDW_SDCA_CTL(fun, ent, ctl, ch) (BIT(30) | \ |
333 |
| - (((fun) & 0x7) << 22) | \ |
334 |
| - (((ent) & 0x40) << 15) | \ |
335 |
| - (((ent) & 0x3f) << 7) | \ |
336 |
| - (((ctl) & 0x30) << 15) | \ |
337 |
| - (((ctl) & 0x0f) << 3) | \ |
338 |
| - (((ch) & 0x38) << 12) | \ |
339 |
| - ((ch) & 0x07)) |
| 335 | +#define SDW_SDCA_CTL(fun, ent, ctl, ch) (BIT(30) | \ |
| 336 | + (((fun) & GENMASK(2, 0)) << 22) | \ |
| 337 | + (((ent) & BIT(6)) << 15) | \ |
| 338 | + (((ent) & GENMASK(5, 0)) << 7) | \ |
| 339 | + (((ctl) & GENMASK(5, 4)) << 15) | \ |
| 340 | + (((ctl) & GENMASK(3, 0)) << 3) | \ |
| 341 | + (((ch) & GENMASK(5, 3)) << 12) | \ |
| 342 | + ((ch) & GENMASK(2, 0))) |
| 343 | + |
| 344 | +#define SDW_SDCA_CTL_FUNC(reg) FIELD_GET(GENMASK(24, 22), (reg)) |
| 345 | +#define SDW_SDCA_CTL_ENT(reg) ((FIELD_GET(BIT(21), (reg)) << 6) | \ |
| 346 | + FIELD_GET(GENMASK(12, 7), (reg))) |
| 347 | +#define SDW_SDCA_CTL_CSEL(reg) ((FIELD_GET(GENMASK(20, 19), (reg)) << 4) | \ |
| 348 | + FIELD_GET(GENMASK(6, 3), (reg))) |
| 349 | +#define SDW_SDCA_CTL_CNUM(reg) ((FIELD_GET(GENMASK(17, 15), (reg)) << 3) | \ |
| 350 | + FIELD_GET(GENMASK(2, 0), (reg))) |
340 | 351 |
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341 | 352 | #define SDW_SDCA_MBQ_CTL(reg) ((reg) | BIT(13))
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342 | 353 | #define SDW_SDCA_NEXT_CTL(reg) ((reg) | BIT(14))
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343 | 354 |
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| 355 | +/* Check the reserved and fixed bits in address */ |
| 356 | +#define SDW_SDCA_VALID_CTL(reg) (((reg) & (GENMASK(31, 25) | BIT(18) | BIT(13))) == BIT(30)) |
| 357 | + |
344 | 358 | #endif /* __SDW_REGISTERS_H */
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