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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Qualcomm Technologies, Inc. NVMEM CPUFreq bindings |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Ilia Lin <ilia.lin@kernel.org> |
| 11 | + |
| 12 | +description: | |
| 13 | + In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply |
| 14 | + voltage is dynamically configured by Core Power Reduction (CPR) depending on |
| 15 | + current CPU frequency and efuse values. |
| 16 | + CPR provides a power domain with multiple levels that are selected depending |
| 17 | + on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level |
| 18 | + according to the required OPPs defined in the CPU OPP tables. |
| 19 | +
|
| 20 | +select: |
| 21 | + properties: |
| 22 | + compatible: |
| 23 | + contains: |
| 24 | + enum: |
| 25 | + - qcom,qcs404 |
| 26 | + required: |
| 27 | + - compatible |
| 28 | + |
| 29 | +properties: |
| 30 | + cpus: |
| 31 | + type: object |
| 32 | + |
| 33 | + patternProperties: |
| 34 | + 'cpu@[0-9a-f]+': |
| 35 | + type: object |
| 36 | + |
| 37 | + properties: |
| 38 | + power-domains: |
| 39 | + maxItems: 1 |
| 40 | + |
| 41 | + power-domain-names: |
| 42 | + items: |
| 43 | + - const: cpr |
| 44 | + |
| 45 | + required: |
| 46 | + - power-domains |
| 47 | + - power-domain-names |
| 48 | + |
| 49 | +patternProperties: |
| 50 | + '^opp-table(-[a-z0-9]+)?$': |
| 51 | + if: |
| 52 | + properties: |
| 53 | + compatible: |
| 54 | + const: operating-points-v2-kryo-cpu |
| 55 | + then: |
| 56 | + patternProperties: |
| 57 | + '^opp-?[0-9]+$': |
| 58 | + required: |
| 59 | + - required-opps |
| 60 | + |
| 61 | +additionalProperties: true |
| 62 | + |
| 63 | +examples: |
| 64 | + - | |
| 65 | + / { |
| 66 | + model = "Qualcomm Technologies, Inc. QCS404"; |
| 67 | + compatible = "qcom,qcs404"; |
| 68 | + #address-cells = <2>; |
| 69 | + #size-cells = <2>; |
| 70 | +
|
| 71 | + cpus { |
| 72 | + #address-cells = <1>; |
| 73 | + #size-cells = <0>; |
| 74 | +
|
| 75 | + CPU0: cpu@100 { |
| 76 | + device_type = "cpu"; |
| 77 | + compatible = "arm,cortex-a53"; |
| 78 | + reg = <0x100>; |
| 79 | + enable-method = "psci"; |
| 80 | + cpu-idle-states = <&CPU_SLEEP_0>; |
| 81 | + next-level-cache = <&L2_0>; |
| 82 | + #cooling-cells = <2>; |
| 83 | + clocks = <&apcs_glb>; |
| 84 | + operating-points-v2 = <&cpu_opp_table>; |
| 85 | + power-domains = <&cpr>; |
| 86 | + power-domain-names = "cpr"; |
| 87 | + }; |
| 88 | +
|
| 89 | + CPU1: cpu@101 { |
| 90 | + device_type = "cpu"; |
| 91 | + compatible = "arm,cortex-a53"; |
| 92 | + reg = <0x101>; |
| 93 | + enable-method = "psci"; |
| 94 | + cpu-idle-states = <&CPU_SLEEP_0>; |
| 95 | + next-level-cache = <&L2_0>; |
| 96 | + #cooling-cells = <2>; |
| 97 | + clocks = <&apcs_glb>; |
| 98 | + operating-points-v2 = <&cpu_opp_table>; |
| 99 | + power-domains = <&cpr>; |
| 100 | + power-domain-names = "cpr"; |
| 101 | + }; |
| 102 | +
|
| 103 | + CPU2: cpu@102 { |
| 104 | + device_type = "cpu"; |
| 105 | + compatible = "arm,cortex-a53"; |
| 106 | + reg = <0x102>; |
| 107 | + enable-method = "psci"; |
| 108 | + cpu-idle-states = <&CPU_SLEEP_0>; |
| 109 | + next-level-cache = <&L2_0>; |
| 110 | + #cooling-cells = <2>; |
| 111 | + clocks = <&apcs_glb>; |
| 112 | + operating-points-v2 = <&cpu_opp_table>; |
| 113 | + power-domains = <&cpr>; |
| 114 | + power-domain-names = "cpr"; |
| 115 | + }; |
| 116 | +
|
| 117 | + CPU3: cpu@103 { |
| 118 | + device_type = "cpu"; |
| 119 | + compatible = "arm,cortex-a53"; |
| 120 | + reg = <0x103>; |
| 121 | + enable-method = "psci"; |
| 122 | + cpu-idle-states = <&CPU_SLEEP_0>; |
| 123 | + next-level-cache = <&L2_0>; |
| 124 | + #cooling-cells = <2>; |
| 125 | + clocks = <&apcs_glb>; |
| 126 | + operating-points-v2 = <&cpu_opp_table>; |
| 127 | + power-domains = <&cpr>; |
| 128 | + power-domain-names = "cpr"; |
| 129 | + }; |
| 130 | + }; |
| 131 | +
|
| 132 | + cpu_opp_table: opp-table-cpu { |
| 133 | + compatible = "operating-points-v2-kryo-cpu"; |
| 134 | + opp-shared; |
| 135 | +
|
| 136 | + opp-1094400000 { |
| 137 | + opp-hz = /bits/ 64 <1094400000>; |
| 138 | + required-opps = <&cpr_opp1>; |
| 139 | + }; |
| 140 | + opp-1248000000 { |
| 141 | + opp-hz = /bits/ 64 <1248000000>; |
| 142 | + required-opps = <&cpr_opp2>; |
| 143 | + }; |
| 144 | + opp-1401600000 { |
| 145 | + opp-hz = /bits/ 64 <1401600000>; |
| 146 | + required-opps = <&cpr_opp3>; |
| 147 | + }; |
| 148 | + }; |
| 149 | +
|
| 150 | + cpr_opp_table: opp-table-cpr { |
| 151 | + compatible = "operating-points-v2-qcom-level"; |
| 152 | +
|
| 153 | + cpr_opp1: opp1 { |
| 154 | + opp-level = <1>; |
| 155 | + qcom,opp-fuse-level = <1>; |
| 156 | + }; |
| 157 | + cpr_opp2: opp2 { |
| 158 | + opp-level = <2>; |
| 159 | + qcom,opp-fuse-level = <2>; |
| 160 | + }; |
| 161 | + cpr_opp3: opp3 { |
| 162 | + opp-level = <3>; |
| 163 | + qcom,opp-fuse-level = <3>; |
| 164 | + }; |
| 165 | + }; |
| 166 | + }; |
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