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Srinivas-Kandagatlabroonie
Srinivas-Kandagatla
authored and
broonie
committed
ASoC: codecs:lpass-wsa-macro: Fix logic of enabling vi channels
Existing code only configures one of WSA_MACRO_TX0 or WSA_MACRO_TX1 paths eventhough we enable both of them. Fix this bug by adding proper checks and rearranging some of the common code to able to allow setting both TX0 and TX1 paths Without this patch only one channel gets enabled in VI path instead of 2 channels. End result would be 1 channel recording instead of 2. Fixes: 2c4066e ("ASoC: codecs: lpass-wsa-macro: add dapm widgets and route") Cc: stable@vger.kernel.org Co-developed-by: Manikantan R <quic_manrav@quicinc.com> Signed-off-by: Manikantan R <quic_manrav@quicinc.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20250403160209.21613-3-srinivas.kandagatla@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
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‎sound/soc/codecs/lpass-wsa-macro.c

Lines changed: 63 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -1459,6 +1459,67 @@ static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable)
14591459
}
14601460
}
14611461

1462+
static void wsa_macro_enable_disable_vi_sense(struct snd_soc_component *component, bool enable,
1463+
u32 tx_reg0, u32 tx_reg1, u32 val)
1464+
{
1465+
if (enable) {
1466+
/* Enable V&I sensing */
1467+
snd_soc_component_update_bits(component, tx_reg0,
1468+
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1469+
CDC_WSA_TX_SPKR_PROT_RESET);
1470+
snd_soc_component_update_bits(component, tx_reg1,
1471+
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1472+
CDC_WSA_TX_SPKR_PROT_RESET);
1473+
snd_soc_component_update_bits(component, tx_reg0,
1474+
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1475+
val);
1476+
snd_soc_component_update_bits(component, tx_reg1,
1477+
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1478+
val);
1479+
snd_soc_component_update_bits(component, tx_reg0,
1480+
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1481+
CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1482+
snd_soc_component_update_bits(component, tx_reg1,
1483+
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1484+
CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1485+
snd_soc_component_update_bits(component, tx_reg0,
1486+
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1487+
CDC_WSA_TX_SPKR_PROT_NO_RESET);
1488+
snd_soc_component_update_bits(component, tx_reg1,
1489+
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1490+
CDC_WSA_TX_SPKR_PROT_NO_RESET);
1491+
} else {
1492+
snd_soc_component_update_bits(component, tx_reg0,
1493+
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1494+
CDC_WSA_TX_SPKR_PROT_RESET);
1495+
snd_soc_component_update_bits(component, tx_reg1,
1496+
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1497+
CDC_WSA_TX_SPKR_PROT_RESET);
1498+
snd_soc_component_update_bits(component, tx_reg0,
1499+
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1500+
CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1501+
snd_soc_component_update_bits(component, tx_reg1,
1502+
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1503+
CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1504+
}
1505+
}
1506+
1507+
static void wsa_macro_enable_disable_vi_feedback(struct snd_soc_component *component,
1508+
bool enable, u32 rate)
1509+
{
1510+
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1511+
1512+
if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI]))
1513+
wsa_macro_enable_disable_vi_sense(component, enable,
1514+
CDC_WSA_TX0_SPKR_PROT_PATH_CTL,
1515+
CDC_WSA_TX1_SPKR_PROT_PATH_CTL, rate);
1516+
1517+
if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI]))
1518+
wsa_macro_enable_disable_vi_sense(component, enable,
1519+
CDC_WSA_TX2_SPKR_PROT_PATH_CTL,
1520+
CDC_WSA_TX3_SPKR_PROT_PATH_CTL, rate);
1521+
}
1522+
14621523
static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w,
14631524
struct snd_kcontrol *kcontrol, int event)
14641525
{
@@ -1475,7 +1536,6 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
14751536
{
14761537
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
14771538
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1478-
u32 tx_reg0, tx_reg1;
14791539
u32 rate_val;
14801540

14811541
switch (wsa->pcm_rate_vi) {
@@ -1499,56 +1559,14 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
14991559
break;
15001560
}
15011561

1502-
if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
1503-
tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL;
1504-
tx_reg1 = CDC_WSA_TX1_SPKR_PROT_PATH_CTL;
1505-
} else if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
1506-
tx_reg0 = CDC_WSA_TX2_SPKR_PROT_PATH_CTL;
1507-
tx_reg1 = CDC_WSA_TX3_SPKR_PROT_PATH_CTL;
1508-
}
1509-
15101562
switch (event) {
15111563
case SND_SOC_DAPM_POST_PMU:
15121564
/* Enable V&I sensing */
1513-
snd_soc_component_update_bits(component, tx_reg0,
1514-
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1515-
CDC_WSA_TX_SPKR_PROT_RESET);
1516-
snd_soc_component_update_bits(component, tx_reg1,
1517-
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1518-
CDC_WSA_TX_SPKR_PROT_RESET);
1519-
snd_soc_component_update_bits(component, tx_reg0,
1520-
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1521-
rate_val);
1522-
snd_soc_component_update_bits(component, tx_reg1,
1523-
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1524-
rate_val);
1525-
snd_soc_component_update_bits(component, tx_reg0,
1526-
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1527-
CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1528-
snd_soc_component_update_bits(component, tx_reg1,
1529-
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1530-
CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1531-
snd_soc_component_update_bits(component, tx_reg0,
1532-
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1533-
CDC_WSA_TX_SPKR_PROT_NO_RESET);
1534-
snd_soc_component_update_bits(component, tx_reg1,
1535-
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1536-
CDC_WSA_TX_SPKR_PROT_NO_RESET);
1565+
wsa_macro_enable_disable_vi_feedback(component, true, rate_val);
15371566
break;
15381567
case SND_SOC_DAPM_POST_PMD:
15391568
/* Disable V&I sensing */
1540-
snd_soc_component_update_bits(component, tx_reg0,
1541-
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1542-
CDC_WSA_TX_SPKR_PROT_RESET);
1543-
snd_soc_component_update_bits(component, tx_reg1,
1544-
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1545-
CDC_WSA_TX_SPKR_PROT_RESET);
1546-
snd_soc_component_update_bits(component, tx_reg0,
1547-
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1548-
CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1549-
snd_soc_component_update_bits(component, tx_reg1,
1550-
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1551-
CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1569+
wsa_macro_enable_disable_vi_feedback(component, false, rate_val);
15521570
break;
15531571
}
15541572

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