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Merge branch 'for-next/cpufeature' into for-next/core
* for-next/cpufeature: kselftest/arm64: Add 2024 dpISA extensions to hwcap test KVM: arm64: Allow control of dpISA extensions in ID_AA64ISAR3_EL1 arm64/hwcap: Describe 2024 dpISA extensions to userspace arm64/sysreg: Update ID_AA64SMFR0_EL1 to DDI0601 2024-12 arm64: Filter out SVE hwcaps when FEAT_SVE isn't implemented arm64/sme: Move storage of reg_smidr to __cpuinfo_store_cpu() arm64/sysreg: Update ID_AA64ISAR2_EL1 to DDI0601 2024-09 arm64/sysreg: Update ID_AA64ZFR0_EL1 to DDI0601 2024-09 arm64/sysreg: Update ID_AA64FPFR0_EL1 to DDI0601 2024-09 arm64/sysreg: Update ID_AA64ISAR3_EL1 to DDI0601 2024-09 arm64/sysreg: Update ID_AA64PFR2_EL1 to DDI0601 2024-09 arm64/sysreg: Get rid of CPACR_ELx SysregFields arm64/sysreg: Convert *_EL12 accessors to Mapping arm64/sysreg: Get rid of the TCR2_EL1x SysregFields arm64/sysreg: Allow a 'Mapping' descriptor for system registers arm64/cpufeature: Refactor conditional logic in init_cpu_ftr_reg() arm64: cpufeature: Add HAFT to cpucap_is_possible()
2 parents f818fd3 + 8600640 commit 763d584

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24 files changed

+585
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lines changed

‎Documentation/arch/arm64/elf_hwcaps.rst

Lines changed: 76 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -174,26 +174,82 @@ HWCAP_GCS
174174
Functionality implied by ID_AA64PFR1_EL1.GCS == 0b1, as
175175
described by Documentation/arch/arm64/gcs.rst.
176176

177+
HWCAP_CMPBR
178+
Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0010.
179+
180+
HWCAP_FPRCVT
181+
Functionality implied by ID_AA64ISAR3_EL1.FPRCVT == 0b0001.
182+
183+
HWCAP_F8MM8
184+
Functionality implied by ID_AA64FPFR0_EL1.F8MM8 == 0b0001.
185+
186+
HWCAP_F8MM4
187+
Functionality implied by ID_AA64FPFR0_EL1.F8MM4 == 0b0001.
188+
189+
HWCAP_SVE_F16MM
190+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
191+
ID_AA64ZFR0_EL1.F16MM == 0b0001.
192+
193+
HWCAP_SVE_ELTPERM
194+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
195+
ID_AA64ZFR0_EL1.ELTPERM == 0b0001.
196+
197+
HWCAP_SVE_AES2
198+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
199+
ID_AA64ZFR0_EL1.AES == 0b0011.
200+
201+
HWCAP_SVE_BFSCALE
202+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
203+
ID_AA64ZFR0_EL1.B16B16 == 0b0010.
204+
205+
HWCAP_SVE2P2
206+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
207+
ID_AA64ZFR0_EL1.SVEver == 0b0011.
208+
209+
HWCAP_SME2P2
210+
Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0011.
211+
212+
HWCAP_SME_SBITPERM
213+
Functionality implied by ID_AA64SMFR0_EL1.SBitPerm == 0b1.
214+
215+
HWCAP_SME_AES
216+
Functionality implied by ID_AA64SMFR0_EL1.AES == 0b1.
217+
218+
HWCAP_SME_SFEXPA
219+
Functionality implied by ID_AA64SMFR0_EL1.SFEXPA == 0b1.
220+
221+
HWCAP_SME_STMOP
222+
Functionality implied by ID_AA64SMFR0_EL1.STMOP == 0b1.
223+
224+
HWCAP_SME_SMOP4
225+
Functionality implied by ID_AA64SMFR0_EL1.SMOP4 == 0b1.
226+
177227
HWCAP2_DCPODP
178228
Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.
179229

180230
HWCAP2_SVE2
181-
Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0001.
231+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
232+
ID_AA64ZFR0_EL1.SVEver == 0b0001.
182233

183234
HWCAP2_SVEAES
184-
Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.
235+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
236+
ID_AA64ZFR0_EL1.AES == 0b0001.
185237

186238
HWCAP2_SVEPMULL
187-
Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.
239+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
240+
ID_AA64ZFR0_EL1.AES == 0b0010.
188241

189242
HWCAP2_SVEBITPERM
190-
Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.
243+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
244+
ID_AA64ZFR0_EL1.BitPerm == 0b0001.
191245

192246
HWCAP2_SVESHA3
193-
Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.
247+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
248+
ID_AA64ZFR0_EL1.SHA3 == 0b0001.
194249

195250
HWCAP2_SVESM4
196-
Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.
251+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
252+
ID_AA64ZFR0_EL1.SM4 == 0b0001.
197253

198254
HWCAP2_FLAGM2
199255
Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.
@@ -202,16 +258,20 @@ HWCAP2_FRINT
202258
Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.
203259

204260
HWCAP2_SVEI8MM
205-
Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001.
261+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
262+
ID_AA64ZFR0_EL1.I8MM == 0b0001.
206263

207264
HWCAP2_SVEF32MM
208-
Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001.
265+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
266+
ID_AA64ZFR0_EL1.F32MM == 0b0001.
209267

210268
HWCAP2_SVEF64MM
211-
Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001.
269+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
270+
ID_AA64ZFR0_EL1.F64MM == 0b0001.
212271

213272
HWCAP2_SVEBF16
214-
Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001.
273+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
274+
ID_AA64ZFR0_EL1.BF16 == 0b0001.
215275

216276
HWCAP2_I8MM
217277
Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.
@@ -277,7 +337,8 @@ HWCAP2_EBF16
277337
Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.
278338

279339
HWCAP2_SVE_EBF16
280-
Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0010.
340+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
341+
ID_AA64ZFR0_EL1.BF16 == 0b0010.
281342

282343
HWCAP2_CSSC
283344
Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001.
@@ -286,7 +347,8 @@ HWCAP2_RPRFM
286347
Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001.
287348

288349
HWCAP2_SVE2P1
289-
Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010.
350+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
351+
ID_AA64ZFR0_EL1.SVEver == 0b0010.
290352

291353
HWCAP2_SME2
292354
Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0001.
@@ -313,7 +375,8 @@ HWCAP2_HBC
313375
Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001.
314376

315377
HWCAP2_SVE_B16B16
316-
Functionality implied by ID_AA64ZFR0_EL1.B16B16 == 0b0001.
378+
Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and
379+
ID_AA64ZFR0_EL1.B16B16 == 0b0001.
317380

318381
HWCAP2_LRCPC3
319382
Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0011.

‎arch/arm64/include/asm/cpucaps.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,8 @@ cpucap_is_possible(const unsigned int cap)
4646
return IS_ENABLED(CONFIG_ARM64_POE);
4747
case ARM64_HAS_GCS:
4848
return IS_ENABLED(CONFIG_ARM64_GCS);
49+
case ARM64_HAFT:
50+
return IS_ENABLED(CONFIG_ARM64_HAFT);
4951
case ARM64_UNMAP_KERNEL_AT_EL0:
5052
return IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0);
5153
case ARM64_WORKAROUND_843419:

‎arch/arm64/include/asm/cpufeature.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -852,8 +852,7 @@ static inline bool system_supports_gcs(void)
852852

853853
static inline bool system_supports_haft(void)
854854
{
855-
return IS_ENABLED(CONFIG_ARM64_HAFT) &&
856-
cpus_have_final_cap(ARM64_HAFT);
855+
return cpus_have_final_cap(ARM64_HAFT);
857856
}
858857

859858
static __always_inline bool system_supports_mpam(void)

‎arch/arm64/include/asm/el2_setup.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,7 @@
154154
/* Coprocessor traps */
155155
.macro __init_el2_cptr
156156
__check_hvhe .LnVHE_\@, x1
157-
mov x0, #CPACR_ELx_FPEN
157+
mov x0, #CPACR_EL1_FPEN
158158
msr cpacr_el1, x0
159159
b .Lskip_set_cptr_\@
160160
.LnVHE_\@:
@@ -332,7 +332,7 @@
332332

333333
// (h)VHE case
334334
mrs x0, cpacr_el1 // Disable SVE traps
335-
orr x0, x0, #CPACR_ELx_ZEN
335+
orr x0, x0, #CPACR_EL1_ZEN
336336
msr cpacr_el1, x0
337337
b .Lskip_set_cptr_\@
338338

@@ -353,7 +353,7 @@
353353

354354
// (h)VHE case
355355
mrs x0, cpacr_el1 // Disable SME traps
356-
orr x0, x0, #CPACR_ELx_SMEN
356+
orr x0, x0, #CPACR_EL1_SMEN
357357
msr cpacr_el1, x0
358358
b .Lskip_set_cptr_sme_\@
359359

‎arch/arm64/include/asm/hwcap.h

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,21 @@
9393
#define KERNEL_HWCAP_PACA __khwcap_feature(PACA)
9494
#define KERNEL_HWCAP_PACG __khwcap_feature(PACG)
9595
#define KERNEL_HWCAP_GCS __khwcap_feature(GCS)
96+
#define KERNEL_HWCAP_CMPBR __khwcap_feature(CMPBR)
97+
#define KERNEL_HWCAP_FPRCVT __khwcap_feature(FPRCVT)
98+
#define KERNEL_HWCAP_F8MM8 __khwcap_feature(F8MM8)
99+
#define KERNEL_HWCAP_F8MM4 __khwcap_feature(F8MM4)
100+
#define KERNEL_HWCAP_SVE_F16MM __khwcap_feature(SVE_F16MM)
101+
#define KERNEL_HWCAP_SVE_ELTPERM __khwcap_feature(SVE_ELTPERM)
102+
#define KERNEL_HWCAP_SVE_AES2 __khwcap_feature(SVE_AES2)
103+
#define KERNEL_HWCAP_SVE_BFSCALE __khwcap_feature(SVE_BFSCALE)
104+
#define KERNEL_HWCAP_SVE2P2 __khwcap_feature(SVE2P2)
105+
#define KERNEL_HWCAP_SME2P2 __khwcap_feature(SME2P2)
106+
#define KERNEL_HWCAP_SME_SBITPERM __khwcap_feature(SME_SBITPERM)
107+
#define KERNEL_HWCAP_SME_AES __khwcap_feature(SME_AES)
108+
#define KERNEL_HWCAP_SME_SFEXPA __khwcap_feature(SME_SFEXPA)
109+
#define KERNEL_HWCAP_SME_STMOP __khwcap_feature(SME_STMOP)
110+
#define KERNEL_HWCAP_SME_SMOP4 __khwcap_feature(SME_SMOP4)
96111

97112
#define __khwcap2_feature(x) (const_ilog2(HWCAP2_ ## x) + 64)
98113
#define KERNEL_HWCAP_DCPODP __khwcap2_feature(DCPODP)

‎arch/arm64/include/asm/kvm_arm.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -391,8 +391,6 @@
391391
ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
392392
ECN(BKPT32), ECN(VECTOR32), ECN(BRK64), ECN(ERET)
393393

394-
#define CPACR_EL1_TTA (1 << 28)
395-
396394
#define kvm_mode_names \
397395
{ PSR_MODE_EL0t, "EL0t" }, \
398396
{ PSR_MODE_EL1t, "EL1t" }, \

‎arch/arm64/include/asm/kvm_emulate.h

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -556,13 +556,13 @@ static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu)
556556
({ \
557557
u64 cptr = 0; \
558558
\
559-
if ((set) & CPACR_ELx_FPEN) \
559+
if ((set) & CPACR_EL1_FPEN) \
560560
cptr |= CPTR_EL2_TFP; \
561-
if ((set) & CPACR_ELx_ZEN) \
561+
if ((set) & CPACR_EL1_ZEN) \
562562
cptr |= CPTR_EL2_TZ; \
563-
if ((set) & CPACR_ELx_SMEN) \
563+
if ((set) & CPACR_EL1_SMEN) \
564564
cptr |= CPTR_EL2_TSM; \
565-
if ((clr) & CPACR_ELx_TTA) \
565+
if ((clr) & CPACR_EL1_TTA) \
566566
cptr |= CPTR_EL2_TTA; \
567567
if ((clr) & CPTR_EL2_TAM) \
568568
cptr |= CPTR_EL2_TAM; \
@@ -576,13 +576,13 @@ static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu)
576576
({ \
577577
u64 cptr = 0; \
578578
\
579-
if ((clr) & CPACR_ELx_FPEN) \
579+
if ((clr) & CPACR_EL1_FPEN) \
580580
cptr |= CPTR_EL2_TFP; \
581-
if ((clr) & CPACR_ELx_ZEN) \
581+
if ((clr) & CPACR_EL1_ZEN) \
582582
cptr |= CPTR_EL2_TZ; \
583-
if ((clr) & CPACR_ELx_SMEN) \
583+
if ((clr) & CPACR_EL1_SMEN) \
584584
cptr |= CPTR_EL2_TSM; \
585-
if ((set) & CPACR_ELx_TTA) \
585+
if ((set) & CPACR_EL1_TTA) \
586586
cptr |= CPTR_EL2_TTA; \
587587
if ((set) & CPTR_EL2_TAM) \
588588
cptr |= CPTR_EL2_TAM; \
@@ -595,13 +595,13 @@ static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu)
595595
#define cpacr_clear_set(clr, set) \
596596
do { \
597597
BUILD_BUG_ON((set) & CPTR_VHE_EL2_RES0); \
598-
BUILD_BUG_ON((clr) & CPACR_ELx_E0POE); \
599-
__build_check_all_or_none((clr), CPACR_ELx_FPEN); \
600-
__build_check_all_or_none((set), CPACR_ELx_FPEN); \
601-
__build_check_all_or_none((clr), CPACR_ELx_ZEN); \
602-
__build_check_all_or_none((set), CPACR_ELx_ZEN); \
603-
__build_check_all_or_none((clr), CPACR_ELx_SMEN); \
604-
__build_check_all_or_none((set), CPACR_ELx_SMEN); \
598+
BUILD_BUG_ON((clr) & CPACR_EL1_E0POE); \
599+
__build_check_all_or_none((clr), CPACR_EL1_FPEN); \
600+
__build_check_all_or_none((set), CPACR_EL1_FPEN); \
601+
__build_check_all_or_none((clr), CPACR_EL1_ZEN); \
602+
__build_check_all_or_none((set), CPACR_EL1_ZEN); \
603+
__build_check_all_or_none((clr), CPACR_EL1_SMEN); \
604+
__build_check_all_or_none((set), CPACR_EL1_SMEN); \
605605
\
606606
if (has_vhe() || has_hvhe()) \
607607
sysreg_clear_set(cpacr_el1, clr, set); \
@@ -624,16 +624,16 @@ static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu)
624624
u64 val;
625625

626626
if (has_vhe()) {
627-
val = (CPACR_ELx_FPEN | CPACR_EL1_ZEN_EL1EN);
627+
val = (CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN);
628628
if (cpus_have_final_cap(ARM64_SME))
629629
val |= CPACR_EL1_SMEN_EL1EN;
630630
} else if (has_hvhe()) {
631-
val = CPACR_ELx_FPEN;
631+
val = CPACR_EL1_FPEN;
632632

633633
if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs())
634-
val |= CPACR_ELx_ZEN;
634+
val |= CPACR_EL1_ZEN;
635635
if (cpus_have_final_cap(ARM64_SME))
636-
val |= CPACR_ELx_SMEN;
636+
val |= CPACR_EL1_SMEN;
637637
} else {
638638
val = CPTR_NVHE_EL2_RES1;
639639

@@ -685,7 +685,7 @@ static inline bool ____cptr_xen_trap_enabled(const struct kvm_vcpu *vcpu,
685685
#define __guest_hyp_cptr_xen_trap_enabled(vcpu, xen) \
686686
(!vcpu_has_nv(vcpu) ? false : \
687687
____cptr_xen_trap_enabled(vcpu, \
688-
SYS_FIELD_GET(CPACR_ELx, xen, \
688+
SYS_FIELD_GET(CPACR_EL1, xen, \
689689
vcpu_sanitised_cptr_el2(vcpu))))
690690

691691
static inline bool guest_hyp_fpsimd_traps_enabled(const struct kvm_vcpu *vcpu)

‎arch/arm64/include/asm/kvm_nested.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -33,14 +33,14 @@ static inline u64 translate_tcr_el2_to_tcr_el1(u64 tcr)
3333

3434
static inline u64 translate_cptr_el2_to_cpacr_el1(u64 cptr_el2)
3535
{
36-
u64 cpacr_el1 = CPACR_ELx_RES1;
36+
u64 cpacr_el1 = CPACR_EL1_RES1;
3737

3838
if (cptr_el2 & CPTR_EL2_TTA)
39-
cpacr_el1 |= CPACR_ELx_TTA;
39+
cpacr_el1 |= CPACR_EL1_TTA;
4040
if (!(cptr_el2 & CPTR_EL2_TFP))
41-
cpacr_el1 |= CPACR_ELx_FPEN;
41+
cpacr_el1 |= CPACR_EL1_FPEN;
4242
if (!(cptr_el2 & CPTR_EL2_TZ))
43-
cpacr_el1 |= CPACR_ELx_ZEN;
43+
cpacr_el1 |= CPACR_EL1_ZEN;
4444

4545
cpacr_el1 |= cptr_el2 & (CPTR_EL2_TCPAC | CPTR_EL2_TAM);
4646

‎arch/arm64/include/uapi/asm/hwcap.h

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,21 @@
5656
#define HWCAP_PACA (1 << 30)
5757
#define HWCAP_PACG (1UL << 31)
5858
#define HWCAP_GCS (1UL << 32)
59+
#define HWCAP_CMPBR (1UL << 33)
60+
#define HWCAP_FPRCVT (1UL << 34)
61+
#define HWCAP_F8MM8 (1UL << 35)
62+
#define HWCAP_F8MM4 (1UL << 36)
63+
#define HWCAP_SVE_F16MM (1UL << 37)
64+
#define HWCAP_SVE_ELTPERM (1UL << 38)
65+
#define HWCAP_SVE_AES2 (1UL << 39)
66+
#define HWCAP_SVE_BFSCALE (1UL << 40)
67+
#define HWCAP_SVE2P2 (1UL << 41)
68+
#define HWCAP_SME2P2 (1UL << 42)
69+
#define HWCAP_SME_SBITPERM (1UL << 43)
70+
#define HWCAP_SME_AES (1UL << 44)
71+
#define HWCAP_SME_SFEXPA (1UL << 45)
72+
#define HWCAP_SME_STMOP (1UL << 46)
73+
#define HWCAP_SME_SMOP4 (1UL << 47)
5974

6075
/*
6176
* HWCAP2 flags - for AT_HWCAP2

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