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alexdeucheralexdeucher
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drm/amdgpu: cache gpu pcie link width
Get the PCIe link with of the device itself (or it's integrated upstream bridge) and cache that. v2: fix typo Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3820 Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent a8d42cd commit 757e8b9

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-32
lines changed

2 files changed

+138
-32
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 120 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -6157,6 +6157,44 @@ static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev,
61576157
}
61586158
}
61596159

6160+
/**
6161+
* amdgpu_device_gpu_bandwidth - find the bandwidth of the GPU
6162+
*
6163+
* @adev: amdgpu_device pointer
6164+
* @speed: pointer to the speed of the link
6165+
* @width: pointer to the width of the link
6166+
*
6167+
* Evaluate the hierarchy to find the speed and bandwidth capabilities of the
6168+
* AMD dGPU which may be a virtual upstream bridge.
6169+
*/
6170+
static void amdgpu_device_gpu_bandwidth(struct amdgpu_device *adev,
6171+
enum pci_bus_speed *speed,
6172+
enum pcie_link_width *width)
6173+
{
6174+
struct pci_dev *parent = adev->pdev;
6175+
6176+
if (!speed || !width)
6177+
return;
6178+
6179+
parent = pci_upstream_bridge(parent);
6180+
if (parent && parent->vendor == PCI_VENDOR_ID_ATI) {
6181+
/* use the upstream/downstream switches internal to dGPU */
6182+
*speed = pcie_get_speed_cap(parent);
6183+
*width = pcie_get_width_cap(parent);
6184+
while ((parent = pci_upstream_bridge(parent))) {
6185+
if (parent->vendor == PCI_VENDOR_ID_ATI) {
6186+
/* use the upstream/downstream switches internal to dGPU */
6187+
*speed = pcie_get_speed_cap(parent);
6188+
*width = pcie_get_width_cap(parent);
6189+
}
6190+
}
6191+
} else {
6192+
/* use the device itself */
6193+
*speed = pcie_get_speed_cap(parent);
6194+
*width = pcie_get_width_cap(parent);
6195+
}
6196+
}
6197+
61606198
/**
61616199
* amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
61626200
*
@@ -6168,9 +6206,8 @@ static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev,
61686206
*/
61696207
static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
61706208
{
6171-
struct pci_dev *pdev;
61726209
enum pci_bus_speed speed_cap, platform_speed_cap;
6173-
enum pcie_link_width platform_link_width;
6210+
enum pcie_link_width platform_link_width, link_width;
61746211

61756212
if (amdgpu_pcie_gen_cap)
61766213
adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
@@ -6192,11 +6229,10 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
61926229

61936230
amdgpu_device_partner_bandwidth(adev, &platform_speed_cap,
61946231
&platform_link_width);
6232+
amdgpu_device_gpu_bandwidth(adev, &speed_cap, &link_width);
61956233

61966234
if (adev->pm.pcie_gen_mask == 0) {
61976235
/* asic caps */
6198-
pdev = adev->pdev;
6199-
speed_cap = pcie_get_speed_cap(pdev);
62006236
if (speed_cap == PCI_SPEED_UNKNOWN) {
62016237
adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
62026238
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
@@ -6252,51 +6288,103 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
62526288
}
62536289
}
62546290
if (adev->pm.pcie_mlw_mask == 0) {
6291+
/* asic caps */
6292+
if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {
6293+
adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_ASIC_PCIE_MLW_MASK;
6294+
} else {
6295+
switch (link_width) {
6296+
case PCIE_LNK_X32:
6297+
adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 |
6298+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 |
6299+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 |
6300+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |
6301+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |
6302+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |
6303+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
6304+
break;
6305+
case PCIE_LNK_X16:
6306+
adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 |
6307+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 |
6308+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |
6309+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |
6310+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |
6311+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
6312+
break;
6313+
case PCIE_LNK_X12:
6314+
adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 |
6315+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |
6316+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |
6317+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |
6318+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
6319+
break;
6320+
case PCIE_LNK_X8:
6321+
adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |
6322+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |
6323+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |
6324+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
6325+
break;
6326+
case PCIE_LNK_X4:
6327+
adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |
6328+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |
6329+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
6330+
break;
6331+
case PCIE_LNK_X2:
6332+
adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |
6333+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
6334+
break;
6335+
case PCIE_LNK_X1:
6336+
adev->pm.pcie_mlw_mask |= CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1;
6337+
break;
6338+
default:
6339+
break;
6340+
}
6341+
}
6342+
/* platform caps */
62556343
if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
62566344
adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
62576345
} else {
62586346
switch (platform_link_width) {
62596347
case PCIE_LNK_X32:
6260-
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
6261-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
6262-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6263-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6264-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6265-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6266-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6348+
adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
6349+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
6350+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6351+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6352+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6353+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6354+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
62676355
break;
62686356
case PCIE_LNK_X16:
6269-
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
6270-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6271-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6272-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6273-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6274-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6357+
adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
6358+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6359+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6360+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6361+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6362+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
62756363
break;
62766364
case PCIE_LNK_X12:
6277-
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6278-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6279-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6280-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6281-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6365+
adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6366+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6367+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6368+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6369+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
62826370
break;
62836371
case PCIE_LNK_X8:
6284-
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6285-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6286-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6287-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6372+
adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6373+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6374+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6375+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
62886376
break;
62896377
case PCIE_LNK_X4:
6290-
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6291-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6292-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6378+
adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6379+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6380+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
62936381
break;
62946382
case PCIE_LNK_X2:
6295-
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6296-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6383+
adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6384+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
62976385
break;
62986386
case PCIE_LNK_X1:
6299-
adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
6387+
adev->pm.pcie_mlw_mask |= CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
63006388
break;
63016389
default:
63026390
break;

‎drivers/gpu/drm/amd/include/amd_pcie.h

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,13 +49,25 @@
4949
| CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
5050

5151
/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
52+
53+
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1 0x00000001
54+
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 0x00000002
55+
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 0x00000004
56+
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 0x00000008
57+
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 0x00000010
58+
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 0x00000020
59+
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 0x00000040
60+
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_MASK 0x0000FFFF
61+
#define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_SHIFT 0
62+
5263
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000
5364
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 0x00020000
5465
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 0x00040000
5566
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 0x00080000
5667
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 0x00100000
5768
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 0x00200000
5869
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 0x00400000
70+
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_MASK 0xFFFF0000
5971
#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT 16
6072

6173
/* 1/2/4/8/16 lanes */
@@ -65,4 +77,10 @@
6577
| CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \
6678
| CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
6779

80+
#define AMDGPU_DEFAULT_ASIC_PCIE_MLW_MASK (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1 \
81+
| CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 \
82+
| CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 \
83+
| CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 \
84+
| CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16)
85+
6886
#endif

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