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Andre-ARMwens
Andre-ARM
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wens
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clk: sunxi-ng: a523: add system mod clocks
Add the clocks driving some core system related subsystems of the SoC: the "CE" crypto engine, the high speed timers, the DRAM and the associated MBUS clock, and the PCIe clock. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-9-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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‎drivers/clk/sunxi-ng/ccu-sun55i-a523.c

Lines changed: 135 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -364,6 +364,21 @@ static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x524,
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24, 3, /* mux */
365365
0);
366366

367+
static const struct clk_parent_data mbus_parents[] = {
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{ .hw = &pll_ddr_clk.common.hw },
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{ .hw = &pll_periph1_600M_clk.hw },
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{ .hw = &pll_periph1_480M_clk.common.hw },
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{ .hw = &pll_periph1_400M_clk.hw },
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{ .hw = &pll_periph1_150M_clk.hw },
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{ .fw_name = "hosc" },
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};
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static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents,
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0x540,
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0, 5, /* M */
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0, 0, /* no P */
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24, 3, /* mux */
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BIT(31), /* gate */
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0, CCU_FEATURE_UPDATE_BIT);
367382

368383
/**************************************************************************
369384
* mod clocks *
@@ -423,6 +438,18 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
423438
BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
425440

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static const struct clk_parent_data ce_parents[] = {
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{ .fw_name = "hosc" },
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{ .hw = &pll_periph0_480M_clk.common.hw },
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{ .hw = &pll_periph0_400M_clk.hw },
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{ .hw = &pll_periph0_300M_clk.hw },
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};
447+
static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
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426453
static const struct clk_hw *ve_parents[] = {
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&pll_ve_clk.common.hw,
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&pll_periph0_480M_clk.common.hw,
@@ -435,6 +462,65 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
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BIT(31), /* gate */
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CLK_SET_RATE_PARENT);
437464

465+
static const struct clk_parent_data hstimer_parents[] = {
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{ .fw_name = "hosc" },
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{ .fw_name = "iosc" },
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{ .fw_name = "losc" },
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{ .hw = &pll_periph0_200M_clk.hw },
470+
};
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static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer0_clk, "hstimer0",
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hstimer_parents, 0x730,
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0, 0, /* M */
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0, 3, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
478+
479+
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer1_clk, "hstimer1",
480+
hstimer_parents,
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0x734,
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0, 0, /* M */
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0, 3, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer2_clk, "hstimer2",
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hstimer_parents,
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0x738,
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0, 0, /* M */
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0, 3, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer3_clk, "hstimer3",
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hstimer_parents,
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0x73c,
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0, 0, /* M */
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0, 3, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
505+
506+
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer4_clk, "hstimer4",
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hstimer_parents,
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0x740,
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0, 0, /* M */
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0, 3, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer5_clk, "hstimer5",
516+
hstimer_parents,
517+
0x744,
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0, 0, /* M */
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0, 3, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
522+
0);
523+
438524
static const struct clk_parent_data iommu_parents[] = {
439525
{ .hw = &pll_periph0_600M_clk.hw },
440526
{ .hw = &pll_ddr_clk.common.hw },
@@ -453,6 +539,34 @@ static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(iommu_clk, "iommu", iommu_parents,
453539
CLK_SET_RATE_PARENT,
454540
CCU_FEATURE_UPDATE_BIT);
455541

542+
static const struct clk_parent_data dram_parents[] = {
543+
{ .hw = &pll_ddr_clk.common.hw },
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{ .hw = &pll_periph0_600M_clk.hw },
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{ .hw = &pll_periph0_480M_clk.common.hw },
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{ .hw = &pll_periph0_400M_clk.hw },
547+
{ .hw = &pll_periph0_150M_clk.hw },
548+
};
549+
static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents,
550+
0x800,
551+
0, 5, /* M */
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0, 0, /* no P */
553+
24, 3, /* mux */
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BIT(31), /* gate */
555+
CLK_IS_CRITICAL,
556+
CCU_FEATURE_UPDATE_BIT);
557+
558+
static const struct clk_parent_data losc_hosc_parents[] = {
559+
{ .fw_name = "hosc" },
560+
{ .fw_name = "losc" },
561+
};
562+
563+
static SUNXI_CCU_M_DATA_WITH_MUX_GATE(pcie_aux_clk, "pcie-aux",
564+
losc_hosc_parents, 0xaa0,
565+
0, 5, /* M */
566+
24, 1, /* mux */
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BIT(31), /* gate */
568+
0);
569+
456570
static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M, 0xb04, BIT(31), 0);
457571

458572
static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k",
@@ -596,12 +710,22 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
596710
&ahb_clk.common,
597711
&apb0_clk.common,
598712
&apb1_clk.common,
713+
&mbus_clk.common,
599714
&de_clk.common,
600715
&di_clk.common,
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&g2d_clk.common,
602717
&gpu_clk.common,
718+
&ce_clk.common,
603719
&ve_clk.common,
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&hstimer0_clk.common,
721+
&hstimer1_clk.common,
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&hstimer2_clk.common,
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&hstimer3_clk.common,
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&hstimer4_clk.common,
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&hstimer5_clk.common,
604726
&iommu_clk.common,
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&dram_clk.common,
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&pcie_aux_clk.common,
605729
&hdmi_24M_clk.common,
606730
&hdmi_cec_32k_clk.common,
607731
&hdmi_cec_clk.common,
@@ -662,11 +786,22 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
662786
[CLK_AHB] = &ahb_clk.common.hw,
663787
[CLK_APB0] = &apb0_clk.common.hw,
664788
[CLK_APB1] = &apb1_clk.common.hw,
789+
[CLK_MBUS] = &mbus_clk.common.hw,
665790
[CLK_DE] = &de_clk.common.hw,
666791
[CLK_DI] = &di_clk.common.hw,
667792
[CLK_G2D] = &g2d_clk.common.hw,
668793
[CLK_GPU] = &gpu_clk.common.hw,
794+
[CLK_CE] = &ce_clk.common.hw,
669795
[CLK_VE] = &ve_clk.common.hw,
796+
[CLK_HSTIMER0] = &hstimer0_clk.common.hw,
797+
[CLK_HSTIMER1] = &hstimer1_clk.common.hw,
798+
[CLK_HSTIMER2] = &hstimer2_clk.common.hw,
799+
[CLK_HSTIMER3] = &hstimer3_clk.common.hw,
800+
[CLK_HSTIMER4] = &hstimer4_clk.common.hw,
801+
[CLK_HSTIMER5] = &hstimer5_clk.common.hw,
802+
[CLK_IOMMU] = &iommu_clk.common.hw,
803+
[CLK_DRAM] = &dram_clk.common.hw,
804+
[CLK_PCIE_AUX] = &pcie_aux_clk.common.hw,
670805
[CLK_HDMI_24M] = &hdmi_24M_clk.common.hw,
671806
[CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.common.hw,
672807
[CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,

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