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Szuying Chendamien-lemoal
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ata: libahci: clear pending interrupt status
When a CRC error occurs, the HBA asserts an interrupt to indicate an interface fatal error (PxIS.IFS). The ISR clears PxIE and PxIS, then does error recovery. If the adapter receives another SDB FIS with an error (PxIS.TFES) from the device before the start of the EH recovery process, the interrupt signaling the new SDB cannot be serviced as PxIE was cleared already. This in turn results in the HBA inability to issue any command during the error recovery process after setting PxCMD.ST to 1 because PxIS.TFES is still set. According to AHCI 1.3.1 specifications section 6.2.2, fatal errors notified by setting PxIS.HBFS, PxIS.HBDS, PxIS.IFS or PxIS.TFES will cause the HBA to enter the ERR:Fatal state. In this state, the HBA shall not issue any new commands. To avoid this situation, introduce the function ahci_port_clear_pending_irq() to clear pending interrupts before executing a COMRESET. This follows the AHCI 1.3.1 - section 6.2.2.2 specification. Signed-off-by: Szuying Chen <Chloe_Chen@asmedia.com.tw> Fixes: e0bfd14 ("[PATCH] ahci: stop engine during hard reset") Cc: stable@vger.kernel.org Reviewed-by: Niklas Cassel <niklas.cassel@wdc.com> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
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drivers/ata/libahci.c

Lines changed: 23 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1256,6 +1256,26 @@ static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
12561256
return sprintf(buf, "%d\n", emp->blink_policy);
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}
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1259+
static void ahci_port_clear_pending_irq(struct ata_port *ap)
1260+
{
1261+
struct ahci_host_priv *hpriv = ap->host->private_data;
1262+
void __iomem *port_mmio = ahci_port_base(ap);
1263+
u32 tmp;
1264+
1265+
/* clear SError */
1266+
tmp = readl(port_mmio + PORT_SCR_ERR);
1267+
dev_dbg(ap->host->dev, "PORT_SCR_ERR 0x%x\n", tmp);
1268+
writel(tmp, port_mmio + PORT_SCR_ERR);
1269+
1270+
/* clear port IRQ */
1271+
tmp = readl(port_mmio + PORT_IRQ_STAT);
1272+
dev_dbg(ap->host->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
1273+
if (tmp)
1274+
writel(tmp, port_mmio + PORT_IRQ_STAT);
1275+
1276+
writel(1 << ap->port_no, hpriv->mmio + HOST_IRQ_STAT);
1277+
}
1278+
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static void ahci_port_init(struct device *dev, struct ata_port *ap,
12601280
int port_no, void __iomem *mmio,
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void __iomem *port_mmio)
@@ -1270,18 +1290,7 @@ static void ahci_port_init(struct device *dev, struct ata_port *ap,
12701290
if (rc)
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dev_warn(dev, "%s (%d)\n", emsg, rc);
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1273-
/* clear SError */
1274-
tmp = readl(port_mmio + PORT_SCR_ERR);
1275-
dev_dbg(dev, "PORT_SCR_ERR 0x%x\n", tmp);
1276-
writel(tmp, port_mmio + PORT_SCR_ERR);
1277-
1278-
/* clear port IRQ */
1279-
tmp = readl(port_mmio + PORT_IRQ_STAT);
1280-
dev_dbg(dev, "PORT_IRQ_STAT 0x%x\n", tmp);
1281-
if (tmp)
1282-
writel(tmp, port_mmio + PORT_IRQ_STAT);
1283-
1284-
writel(1 << port_no, mmio + HOST_IRQ_STAT);
1293+
ahci_port_clear_pending_irq(ap);
12851294

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/* mark esata ports */
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tmp = readl(port_mmio + PORT_CMD);
@@ -1603,6 +1612,8 @@ int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
16031612
tf.status = ATA_BUSY;
16041613
ata_tf_to_fis(&tf, 0, 0, d2h_fis);
16051614

1615+
ahci_port_clear_pending_irq(ap);
1616+
16061617
rc = sata_link_hardreset(link, timing, deadline, online,
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ahci_check_ready);
16081619

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