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pixelclusteralexdeucher
pixelcluster
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alexdeucher
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drm/amdgpu: Reset IH OVERFLOW_CLEAR bit
Allows us to detect subsequent IH ring buffer overflows as well. Cc: Joshua Ashton <joshua@froggi.es> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Friedrich Vock <friedrich.vock@gmx.de> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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‎drivers/gpu/drm/amd/amdgpu/cik_ih.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -204,6 +204,12 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
204204
tmp = RREG32(mmIH_RB_CNTL);
205205
tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
206206
WREG32(mmIH_RB_CNTL, tmp);
207+
208+
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
209+
* can be detected.
210+
*/
211+
tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
212+
WREG32(mmIH_RB_CNTL, tmp);
207213
}
208214
return (wptr & ih->ptr_mask);
209215
}

‎drivers/gpu/drm/amd/amdgpu/cz_ih.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -216,6 +216,11 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
216216
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
217217
WREG32(mmIH_RB_CNTL, tmp);
218218

219+
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
220+
* can be detected.
221+
*/
222+
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
223+
WREG32(mmIH_RB_CNTL, tmp);
219224

220225
out:
221226
return (wptr & ih->ptr_mask);

‎drivers/gpu/drm/amd/amdgpu/iceland_ih.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -215,6 +215,11 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev,
215215
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
216216
WREG32(mmIH_RB_CNTL, tmp);
217217

218+
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
219+
* can be detected.
220+
*/
221+
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
222+
WREG32(mmIH_RB_CNTL, tmp);
218223

219224
out:
220225
return (wptr & ih->ptr_mask);

‎drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -418,6 +418,12 @@ static u32 ih_v6_0_get_wptr(struct amdgpu_device *adev,
418418
tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
419419
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
420420
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
421+
422+
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
423+
* can be detected.
424+
*/
425+
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
426+
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
421427
out:
422428
return (wptr & ih->ptr_mask);
423429
}

‎drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -418,6 +418,13 @@ static u32 ih_v6_1_get_wptr(struct amdgpu_device *adev,
418418
tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
419419
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
420420
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
421+
422+
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
423+
* can be detected.
424+
*/
425+
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
426+
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
427+
421428
out:
422429
return (wptr & ih->ptr_mask);
423430
}

‎drivers/gpu/drm/amd/amdgpu/navi10_ih.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -442,6 +442,12 @@ static u32 navi10_ih_get_wptr(struct amdgpu_device *adev,
442442
tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
443443
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
444444
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
445+
446+
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
447+
* can be detected.
448+
*/
449+
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
450+
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
445451
out:
446452
return (wptr & ih->ptr_mask);
447453
}

‎drivers/gpu/drm/amd/amdgpu/si_ih.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,12 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev,
119119
tmp = RREG32(IH_RB_CNTL);
120120
tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
121121
WREG32(IH_RB_CNTL, tmp);
122+
123+
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
124+
* can be detected.
125+
*/
126+
tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
127+
WREG32(IH_RB_CNTL, tmp);
122128
}
123129
return (wptr & ih->ptr_mask);
124130
}

‎drivers/gpu/drm/amd/amdgpu/tonga_ih.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -219,6 +219,12 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
219219
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
220220
WREG32(mmIH_RB_CNTL, tmp);
221221

222+
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
223+
* can be detected.
224+
*/
225+
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
226+
WREG32(mmIH_RB_CNTL, tmp);
227+
222228
out:
223229
return (wptr & ih->ptr_mask);
224230
}

‎drivers/gpu/drm/amd/amdgpu/vega10_ih.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -373,6 +373,12 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
373373
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
374374
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
375375

376+
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
377+
* can be detected.
378+
*/
379+
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
380+
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
381+
376382
out:
377383
return (wptr & ih->ptr_mask);
378384
}

‎drivers/gpu/drm/amd/amdgpu/vega20_ih.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -421,6 +421,12 @@ static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
421421
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
422422
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
423423

424+
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
425+
* can be detected.
426+
*/
427+
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
428+
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
429+
424430
out:
425431
return (wptr & ih->ptr_mask);
426432
}

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