Skip to content

Commit 708283a

Browse files
torvaldstorvalds
committed
Merge tag 'dmaengine-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul: "New controller support and updates to drivers. New support: - Qualcomm SM6115 and QCM2290 dmaengine support - at_xdma support for microchip,sam9x7 controller Updates: - idxd updates for wq simplification and ats knob updates - fsl edma updates for v3 support - Xilinx AXI4-Stream control support - Yaml conversion for bcm dma binding" * tag 'dmaengine-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (53 commits) dmaengine: fsl-edma: integrate v3 support dt-bindings: fsl-dma: fsl-edma: add edma3 compatible string dmaengine: fsl-edma: move tcd into struct fsl_dma_chan dmaengine: fsl-edma: refactor chan_name setup and safety dmaengine: fsl-edma: move clearing of register interrupt into setup_irq function dmaengine: fsl-edma: refactor using devm_clk_get_enabled dmaengine: fsl-edma: simply ATTR_DSIZE and ATTR_SSIZE by using ffs() dmaengine: fsl-edma: move common IRQ handler to common.c dmaengine: fsl-edma: Remove enum edma_version dmaengine: fsl-edma: transition from bool fields to bitmask flags in drvdata dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.c dmaengine: fsl-edma: fix build error when arch is s390 dmaengine: idxd: Fix issues with PRS disable sysfs knob dmaengine: idxd: Allow ATS disable update only for configurable devices dmaengine: xilinx_dma: Program interrupt delay timeout dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecase dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit dmaengine: xilinx_dma: Increase AXI DMA transaction segment count dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property ...
2 parents db906f0 + 72f5801 commit 708283a

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

71 files changed

+998
-2871
lines changed

‎Documentation/ABI/stable/sysfs-driver-dma-idxd

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@ What: /sys/bus/dsa/devices/dsa<m>/pasid_enabled
8484
Date: Oct 27, 2020
8585
KernelVersion: 5.11.0
8686
Contact: dmaengine@vger.kernel.org
87-
Description: To indicate if PASID (process address space identifier) is
87+
Description: To indicate if user PASID (process address space identifier) is
8888
enabled or not for this device.
8989

9090
What: /sys/bus/dsa/devices/dsa<m>/state

‎Documentation/devicetree/bindings/dma/atmel-xdma.txt

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,8 @@
33
* XDMA Controller
44
Required properties:
55
- compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or
6-
"microchip,sama7g5-dma".
6+
"microchip,sama7g5-dma" or
7+
"microchip,sam9x7-dma", "atmel,sama5d4-dma".
78
- reg: Should contain DMA registers location and length.
89
- interrupts: Should contain DMA interrupt.
910
- #dma-cells: Must be <1>, used to represent the number of integer cells in

‎Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt

Lines changed: 0 additions & 83 deletions
This file was deleted.

‎Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.yaml

Lines changed: 102 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,102 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/dma/brcm,bcm2835-dma.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: BCM2835 DMA controller
8+
9+
maintainers:
10+
- Nicolas Saenz Julienne <nsaenz@kernel.org>
11+
12+
description:
13+
The BCM2835 DMA controller has 16 channels in total. Only the lower
14+
13 channels have an associated IRQ. Some arbitrary channels are used by the
15+
VideoCore firmware (1,3,6,7 in the current firmware version). The channels
16+
0, 2 and 3 have special functionality and should not be used by the driver.
17+
18+
allOf:
19+
- $ref: dma-controller.yaml#
20+
21+
properties:
22+
compatible:
23+
const: brcm,bcm2835-dma
24+
25+
reg:
26+
maxItems: 1
27+
28+
interrupts:
29+
description:
30+
Should contain the DMA interrupts associated to the DMA channels in
31+
ascending order.
32+
minItems: 1
33+
maxItems: 16
34+
35+
interrupt-names:
36+
minItems: 1
37+
maxItems: 16
38+
39+
'#dma-cells':
40+
description: The single cell represents the DREQ number.
41+
const: 1
42+
43+
brcm,dma-channel-mask:
44+
$ref: /schemas/types.yaml#/definitions/uint32
45+
description:
46+
Bitmask of available DMA channels in ascending order that are
47+
not reserved by firmware and are available to the
48+
kernel. i.e. first channel corresponds to LSB.
49+
50+
unevaluatedProperties: false
51+
52+
required:
53+
- compatible
54+
- reg
55+
- interrupts
56+
- "#dma-cells"
57+
- brcm,dma-channel-mask
58+
59+
examples:
60+
- |
61+
dma-controller@7e007000 {
62+
compatible = "brcm,bcm2835-dma";
63+
reg = <0x7e007000 0xf00>;
64+
interrupts = <1 16>,
65+
<1 17>,
66+
<1 18>,
67+
<1 19>,
68+
<1 20>,
69+
<1 21>,
70+
<1 22>,
71+
<1 23>,
72+
<1 24>,
73+
<1 25>,
74+
<1 26>,
75+
/* dma channel 11-14 share one irq */
76+
<1 27>,
77+
<1 27>,
78+
<1 27>,
79+
<1 27>,
80+
/* unused shared irq for all channels */
81+
<1 28>;
82+
interrupt-names = "dma0",
83+
"dma1",
84+
"dma2",
85+
"dma3",
86+
"dma4",
87+
"dma5",
88+
"dma6",
89+
"dma7",
90+
"dma8",
91+
"dma9",
92+
"dma10",
93+
"dma11",
94+
"dma12",
95+
"dma13",
96+
"dma14",
97+
"dma-shared-all";
98+
#dma-cells = <1>;
99+
brcm,dma-channel-mask = <0x7f35>;
100+
};
101+
102+
...

‎Documentation/devicetree/bindings/dma/fsl,edma.yaml

Lines changed: 99 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -21,32 +21,41 @@ properties:
2121
- enum:
2222
- fsl,vf610-edma
2323
- fsl,imx7ulp-edma
24+
- fsl,imx8qm-adma
25+
- fsl,imx8qm-edma
26+
- fsl,imx93-edma3
27+
- fsl,imx93-edma4
2428
- items:
2529
- const: fsl,ls1028a-edma
2630
- const: fsl,vf610-edma
2731

2832
reg:
29-
minItems: 2
33+
minItems: 1
3034
maxItems: 3
3135

3236
interrupts:
33-
minItems: 2
34-
maxItems: 17
37+
minItems: 1
38+
maxItems: 64
3539

3640
interrupt-names:
37-
minItems: 2
38-
maxItems: 17
41+
minItems: 1
42+
maxItems: 64
3943

4044
"#dma-cells":
41-
const: 2
45+
enum:
46+
- 2
47+
- 3
4248

4349
dma-channels:
44-
const: 32
50+
minItems: 1
51+
maxItems: 64
4552

4653
clocks:
54+
minItems: 1
4755
maxItems: 2
4856

4957
clock-names:
58+
minItems: 1
5059
maxItems: 2
5160

5261
big-endian:
@@ -65,25 +74,56 @@ required:
6574

6675
allOf:
6776
- $ref: dma-controller.yaml#
77+
- if:
78+
properties:
79+
compatible:
80+
contains:
81+
enum:
82+
- fsl,imx8qm-adma
83+
- fsl,imx8qm-edma
84+
- fsl,imx93-edma3
85+
- fsl,imx93-edma4
86+
then:
87+
properties:
88+
"#dma-cells":
89+
const: 3
90+
# It is not necessary to write the interrupt name for each channel.
91+
# instead, you can simply maintain the sequential IRQ numbers as
92+
# defined for the DMA channels.
93+
interrupt-names: false
94+
clock-names:
95+
items:
96+
- const: dma
97+
clocks:
98+
maxItems: 1
99+
68100
- if:
69101
properties:
70102
compatible:
71103
contains:
72104
const: fsl,vf610-edma
73105
then:
74106
properties:
107+
clocks:
108+
minItems: 2
75109
clock-names:
76110
items:
77111
- const: dmamux0
78112
- const: dmamux1
79113
interrupts:
114+
minItems: 2
80115
maxItems: 2
81116
interrupt-names:
82117
items:
83118
- const: edma-tx
84119
- const: edma-err
85120
reg:
121+
minItems: 2
86122
maxItems: 3
123+
"#dma-cells":
124+
const: 2
125+
dma-channels:
126+
const: 32
87127

88128
- if:
89129
properties:
@@ -92,14 +132,22 @@ allOf:
92132
const: fsl,imx7ulp-edma
93133
then:
94134
properties:
135+
clock:
136+
minItems: 2
95137
clock-names:
96138
items:
97139
- const: dma
98140
- const: dmamux0
99141
interrupts:
142+
minItems: 2
100143
maxItems: 17
101144
reg:
145+
minItems: 2
102146
maxItems: 2
147+
"#dma-cells":
148+
const: 2
149+
dma-channels:
150+
const: 32
103151

104152
unevaluatedProperties: false
105153

@@ -153,3 +201,47 @@ examples:
153201
clock-names = "dma", "dmamux0";
154202
clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
155203
};
204+
205+
- |
206+
#include <dt-bindings/interrupt-controller/arm-gic.h>
207+
#include <dt-bindings/clock/imx93-clock.h>
208+
209+
dma-controller@44000000 {
210+
compatible = "fsl,imx93-edma3";
211+
reg = <0x44000000 0x200000>;
212+
#dma-cells = <3>;
213+
dma-channels = <31>;
214+
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
215+
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
216+
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
217+
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
218+
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
219+
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
220+
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
221+
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
222+
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
223+
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
224+
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
225+
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
226+
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
227+
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
228+
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
229+
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
230+
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
231+
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
232+
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
233+
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
234+
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
235+
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
236+
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
237+
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
238+
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
239+
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
240+
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
241+
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
242+
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
243+
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
244+
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
245+
clocks = <&clk IMX93_CLK_EDMA1_GATE>;
246+
clock-names = "dma";
247+
};

0 commit comments

Comments
 (0)