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petegriffin
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pinctrl: samsung: add support for eint_fltcon_offset
On gs101 SoC the fltcon0 (filter configuration 0) offset isn't at a fixed offset like previous SoCs as the fltcon1 register only exists when there are more than 4 pins in the bank. Add a eint_fltcon_offset and new GS101_PIN_BANK_EINT* macros that take an additional fltcon_offs variable. This can then be used in suspend/resume callbacks to save and restore the fltcon0 and fltcon1 registers. Fixes: 4a8be01 ("pinctrl: samsung: Add gs101 SoC pinctrl configuration") Cc: stable@vger.kernel.org Reviewed-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250307-pinctrl-fltcon-suspend-v4-1-2d775e486036@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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‎drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

Lines changed: 49 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -1677,83 +1677,83 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
16771677

16781678
/* pin banks of gs101 pin-controller (ALIVE) */
16791679
static const struct samsung_pin_bank_data gs101_pin_alive[] = {
1680-
EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00),
1681-
EXYNOS850_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04),
1682-
EXYNOS850_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08),
1683-
EXYNOS850_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c),
1684-
EXYNOS850_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10),
1685-
EXYNOS850_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14),
1686-
EXYNOS850_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18),
1687-
EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c),
1680+
GS101_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00, 0x00),
1681+
GS101_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04, 0x08),
1682+
GS101_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08, 0x10),
1683+
GS101_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c, 0x18),
1684+
GS101_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10, 0x1c),
1685+
GS101_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14, 0x20),
1686+
GS101_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18, 0x28),
1687+
GS101_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c, 0x30),
16881688
};
16891689

16901690
/* pin banks of gs101 pin-controller (FAR_ALIVE) */
16911691
static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
1692-
EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00),
1693-
EXYNOS850_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04),
1694-
EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08),
1695-
EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c),
1692+
GS101_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00, 0x00),
1693+
GS101_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04, 0x08),
1694+
GS101_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08, 0x0c),
1695+
GS101_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c, 0x14),
16961696
};
16971697

16981698
/* pin banks of gs101 pin-controller (GSACORE) */
16991699
static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
1700-
EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00),
1701-
EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04),
1702-
EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08),
1700+
GS101_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00, 0x00),
1701+
GS101_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04, 0x04),
1702+
GS101_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08, 0x0c),
17031703
};
17041704

17051705
/* pin banks of gs101 pin-controller (GSACTRL) */
17061706
static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
1707-
EXYNOS850_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00),
1707+
GS101_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00, 0x00),
17081708
};
17091709

17101710
/* pin banks of gs101 pin-controller (PERIC0) */
17111711
static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
1712-
EXYNOS850_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00),
1713-
EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04),
1714-
EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08),
1715-
EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c),
1716-
EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10),
1717-
EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14),
1718-
EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18),
1719-
EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c),
1720-
EXYNOS850_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20),
1721-
EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24),
1722-
EXYNOS850_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28),
1723-
EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c),
1724-
EXYNOS850_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30),
1725-
EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34),
1726-
EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38),
1727-
EXYNOS850_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c),
1728-
EXYNOS850_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40),
1729-
EXYNOS850_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44),
1730-
EXYNOS850_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48),
1731-
EXYNOS850_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c),
1712+
GS101_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00, 0x00),
1713+
GS101_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04, 0x08),
1714+
GS101_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08, 0x0c),
1715+
GS101_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c, 0x10),
1716+
GS101_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10, 0x14),
1717+
GS101_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14, 0x18),
1718+
GS101_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18, 0x1c),
1719+
GS101_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c, 0x20),
1720+
GS101_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20, 0x24),
1721+
GS101_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24, 0x28),
1722+
GS101_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28, 0x2c),
1723+
GS101_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c, 0x30),
1724+
GS101_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30, 0x34),
1725+
GS101_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34, 0x38),
1726+
GS101_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38, 0x3c),
1727+
GS101_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c, 0x40),
1728+
GS101_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40, 0x44),
1729+
GS101_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44, 0x48),
1730+
GS101_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48, 0x4c),
1731+
GS101_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c, 0x50),
17321732
};
17331733

17341734
/* pin banks of gs101 pin-controller (PERIC1) */
17351735
static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
1736-
EXYNOS850_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00),
1737-
EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04),
1738-
EXYNOS850_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08),
1739-
EXYNOS850_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c),
1740-
EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10),
1741-
EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14),
1742-
EXYNOS850_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18),
1743-
EXYNOS850_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c),
1736+
GS101_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00, 0x00),
1737+
GS101_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04, 0x08),
1738+
GS101_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08, 0x0c),
1739+
GS101_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c, 0x10),
1740+
GS101_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10, 0x18),
1741+
GS101_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14, 0x1c),
1742+
GS101_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18, 0x20),
1743+
GS101_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c, 0x28),
17441744
};
17451745

17461746
/* pin banks of gs101 pin-controller (HSI1) */
17471747
static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
1748-
EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00),
1749-
EXYNOS850_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04),
1748+
GS101_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00, 0x00),
1749+
GS101_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04, 0x08),
17501750
};
17511751

17521752
/* pin banks of gs101 pin-controller (HSI2) */
17531753
static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
1754-
EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00),
1755-
EXYNOS850_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04),
1756-
EXYNOS850_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08),
1754+
GS101_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00, 0x00),
1755+
GS101_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04, 0x08),
1756+
GS101_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08, 0x0c),
17571757
};
17581758

17591759
static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {

‎drivers/pinctrl/samsung/pinctrl-exynos.h

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -194,6 +194,28 @@
194194
.name = id \
195195
}
196196

197+
#define GS101_PIN_BANK_EINTG(pins, reg, id, offs, fltcon_offs) \
198+
{ \
199+
.type = &exynos850_bank_type_off, \
200+
.pctl_offset = reg, \
201+
.nr_pins = pins, \
202+
.eint_type = EINT_TYPE_GPIO, \
203+
.eint_offset = offs, \
204+
.eint_fltcon_offset = fltcon_offs, \
205+
.name = id \
206+
}
207+
208+
#define GS101_PIN_BANK_EINTW(pins, reg, id, offs, fltcon_offs) \
209+
{ \
210+
.type = &exynos850_bank_type_alive, \
211+
.pctl_offset = reg, \
212+
.nr_pins = pins, \
213+
.eint_type = EINT_TYPE_WKUP, \
214+
.eint_offset = offs, \
215+
.eint_fltcon_offset = fltcon_offs, \
216+
.name = id \
217+
}
218+
197219
/**
198220
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
199221
* generated by the external wakeup interrupt controller.

‎drivers/pinctrl/samsung/pinctrl-samsung.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1230,6 +1230,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
12301230
bank->eint_con_offset = bdata->eint_con_offset;
12311231
bank->eint_mask_offset = bdata->eint_mask_offset;
12321232
bank->eint_pend_offset = bdata->eint_pend_offset;
1233+
bank->eint_fltcon_offset = bdata->eint_fltcon_offset;
12331234
bank->name = bdata->name;
12341235

12351236
raw_spin_lock_init(&bank->slock);

‎drivers/pinctrl/samsung/pinctrl-samsung.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,7 @@ struct samsung_pin_bank_type {
144144
* @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.
145145
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
146146
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
147+
* @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
147148
* @name: name to be prefixed for each pin in this pin bank.
148149
*/
149150
struct samsung_pin_bank_data {
@@ -158,6 +159,7 @@ struct samsung_pin_bank_data {
158159
u32 eint_con_offset;
159160
u32 eint_mask_offset;
160161
u32 eint_pend_offset;
162+
u32 eint_fltcon_offset;
161163
const char *name;
162164
};
163165

@@ -175,6 +177,7 @@ struct samsung_pin_bank_data {
175177
* @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.
176178
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
177179
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
180+
* @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
178181
* @name: name to be prefixed for each pin in this pin bank.
179182
* @id: id of the bank, propagated to the pin range.
180183
* @pin_base: starting pin number of the bank.
@@ -201,6 +204,7 @@ struct samsung_pin_bank {
201204
u32 eint_con_offset;
202205
u32 eint_mask_offset;
203206
u32 eint_pend_offset;
207+
u32 eint_fltcon_offset;
204208
const char *name;
205209
u32 id;
206210

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