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Merge tag 'irq-core-2024-05-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull interrupt subsystem updates from Thomas Gleixner: "Core code: - Interrupt storm detection for the lockup watchdog: Lockups which are caused by interrupt storms are not easy to debug because there is no information about the events which make the lockup detector trigger. To make this more user friendly, provide an extenstion to interrupt statistics which allows to take snapshots and an interface to retrieve the delta to the snapshot. Use this new mechanism in the watchdog code to do a two stage lockup analysis by taking the snapshot and printing the deltas for the topmost active interrupts on the second trigger. Note: This contains both the interrupt and the watchdog changes as the latter depend on the former obviously. - Avoid summation loops in the /proc/interrupts output and use the global counter when possible - Skip suspended interrupts on CPU hotplug operations to ensure that they are not delivered before the system resumes the device drivers when coming out of suspend. - On CPU hot-unplug interrupts which are affine to the outgoing CPU are migrated to a different CPU in the affinity mask. This can fail when the CPUs have no vectors left. Instead of giving up try to migrate it to any online CPU and thereby breaking the affinity setting in order to prevent a stale device interrupt which targets an offline CPU - The usual small cleanups Driver code: - Support for the RISCV AIA MSI controller - Make the interrupt allocation for the Loongson PCH controller more flexible to prevent vector exhaustion - The usual set of cleanups and fixes all over the place" * tag 'irq-core-2024-05-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (51 commits) irqchip/gic-v3-its: Remove BUG_ON in its_vpe_irq_domain_alloc cpuidle: Avoid explicit cpumask allocation on stack irqchip/sifive-plic: Avoid explicit cpumask allocation on stack irqchip/riscv-aplic-direct: Avoid explicit cpumask allocation on stack irqchip/loongson-eiointc: Avoid explicit cpumask allocation on stack irqchip/gic-v3-its: Avoid explicit cpumask allocation on stack irqchip/irq-bcm6345-l1: Avoid explicit cpumask allocation on stack cpumask: Introduce cpumask_first_and_and() irqchip/irq-brcmstb-l2: Avoid saving mask on shutdown genirq: Reuse irq_is_nmi() genirq/cpuhotplug: Retry with cpu_online_mask when migration fails genirq/cpuhotplug: Skip suspended interrupts when restoring affinity arm64: dts: st: Add interrupt parent to pinctrl on stm32mp251 arm64: dts: st: Add exti1 and exti2 nodes on stm32mp251 ARM: dts: stm32: List exti parent interrupts on stm32mp131 ARM: dts: stm32: List exti parent interrupts on stm32mp151 arm64: Kconfig.platforms: Enable STM32_EXTI for ARCH_STM32 irqchip/stm32-exti: Mark events reserved with RIF configuration check irqchip/stm32-exti: Skip secure events irqchip/stm32-exti: Convert driver to standard PM ...
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‎Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
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maintainers:
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- Anup Patel <anup@brainfault.org>
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description:
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The RISC-V advanced interrupt architecture (AIA) defines an advanced
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platform level interrupt controller (APLIC) for handling wired interrupts
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in a RISC-V platform. The RISC-V AIA specification can be found at
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https://github.com/riscv/riscv-aia.
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The RISC-V APLIC is implemented as hierarchical APLIC domains where all
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interrupt sources connect to the root APLIC domain and a parent APLIC
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domain can delegate interrupt sources to it's child APLIC domains. There
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is one device tree node for each APLIC domain.
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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items:
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- enum:
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- qemu,aplic
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- const: riscv,aplic
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reg:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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interrupts-extended:
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minItems: 1
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maxItems: 16384
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description:
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Given APLIC domain directly injects external interrupts to a set of
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RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
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node, which has a CPU node (i.e. RISC-V HART) as parent.
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msi-parent:
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description:
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Given APLIC domain forwards wired interrupts as MSIs to a AIA incoming
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message signaled interrupt controller (IMSIC). If both "msi-parent" and
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"interrupts-extended" properties are present then it means the APLIC
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domain supports both MSI mode and Direct mode in HW. In this case, the
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APLIC driver has to choose between MSI mode or Direct mode.
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riscv,num-sources:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 1023
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description:
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Specifies the number of wired interrupt sources supported by this
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APLIC domain.
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riscv,children:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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minItems: 1
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maxItems: 1024
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items:
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maxItems: 1
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description:
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A list of child APLIC domains for the given APLIC domain. Each child
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APLIC domain is assigned a child index in increasing order, with the
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first child APLIC domain assigned child index 0. The APLIC domain child
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index is used by firmware to delegate interrupts from the given APLIC
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domain to a particular child APLIC domain.
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riscv,delegation:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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minItems: 1
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maxItems: 1024
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items:
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items:
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- description: child APLIC domain phandle
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- description: first interrupt number of the parent APLIC domain (inclusive)
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- description: last interrupt number of the parent APLIC domain (inclusive)
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description:
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A interrupt delegation list where each entry is a triple consisting
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of child APLIC domain phandle, first interrupt number of the parent
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APLIC domain, and last interrupt number of the parent APLIC domain.
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Firmware must configure interrupt delegation registers based on
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interrupt delegation list.
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dependencies:
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riscv,delegation: [ "riscv,children" ]
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required:
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- compatible
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- reg
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- interrupt-controller
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- "#interrupt-cells"
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- riscv,num-sources
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anyOf:
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- required:
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- interrupts-extended
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- required:
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- msi-parent
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unevaluatedProperties: false
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examples:
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- |
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// Example 1 (APLIC domains directly injecting interrupt to HARTs):
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interrupt-controller@c000000 {
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compatible = "qemu,aplic", "riscv,aplic";
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interrupts-extended = <&cpu1_intc 11>,
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<&cpu2_intc 11>,
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<&cpu3_intc 11>,
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<&cpu4_intc 11>;
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reg = <0xc000000 0x4080>;
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interrupt-controller;
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#interrupt-cells = <2>;
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riscv,num-sources = <63>;
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riscv,children = <&aplic1>, <&aplic2>;
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riscv,delegation = <&aplic1 1 63>;
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};
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aplic1: interrupt-controller@d000000 {
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compatible = "qemu,aplic", "riscv,aplic";
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interrupts-extended = <&cpu1_intc 9>,
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<&cpu2_intc 9>;
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reg = <0xd000000 0x4080>;
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interrupt-controller;
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#interrupt-cells = <2>;
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riscv,num-sources = <63>;
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};
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aplic2: interrupt-controller@e000000 {
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compatible = "qemu,aplic", "riscv,aplic";
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interrupts-extended = <&cpu3_intc 9>,
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<&cpu4_intc 9>;
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reg = <0xe000000 0x4080>;
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interrupt-controller;
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#interrupt-cells = <2>;
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riscv,num-sources = <63>;
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};
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- |
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// Example 2 (APLIC domains forwarding interrupts as MSIs):
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interrupt-controller@c000000 {
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compatible = "qemu,aplic", "riscv,aplic";
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msi-parent = <&imsic_mlevel>;
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reg = <0xc000000 0x4000>;
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interrupt-controller;
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#interrupt-cells = <2>;
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riscv,num-sources = <63>;
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riscv,children = <&aplic3>;
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riscv,delegation = <&aplic3 1 63>;
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};
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aplic3: interrupt-controller@d000000 {
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compatible = "qemu,aplic", "riscv,aplic";
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msi-parent = <&imsic_slevel>;
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reg = <0xd000000 0x4000>;
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interrupt-controller;
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#interrupt-cells = <2>;
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riscv,num-sources = <63>;
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};
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...

‎Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: RISC-V Incoming MSI Controller (IMSIC)
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maintainers:
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- Anup Patel <anup@brainfault.org>
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description: |
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The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
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MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
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AIA specification can be found at https://github.com/riscv/riscv-aia.
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The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
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for each privilege level (machine or supervisor). The configuration of
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a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO
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space to receive MSIs from devices. Each IMSIC interrupt file supports a
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fixed number of interrupt identities (to distinguish MSIs from devices)
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which is same for given privilege level across CPUs (or HARTs).
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The device tree of a RISC-V platform will have one IMSIC device tree node
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for each privilege level (machine or supervisor) which collectively describe
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IMSIC interrupt files at that privilege level across CPUs (or HARTs).
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The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform
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follows a particular scheme defined by the RISC-V AIA specification. A IMSIC
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group is a set of IMSIC interrupt files co-located in MMIO space and we can
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have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a
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RISC-V platform. The MSI target address of a IMSIC interrupt file at given
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privilege level (machine or supervisor) encodes group index, HART index,
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and guest index (shown below).
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XLEN-1 > (HART Index MSB) 12 0
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| | | |
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-------------------------------------------------------------
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|xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
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-------------------------------------------------------------
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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- $ref: /schemas/interrupt-controller/msi-controller.yaml#
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properties:
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compatible:
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items:
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- enum:
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- qemu,imsics
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- const: riscv,imsics
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reg:
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minItems: 1
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maxItems: 16384
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description:
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Base address of each IMSIC group.
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interrupt-controller: true
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"#interrupt-cells":
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const: 0
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msi-controller: true
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"#msi-cells":
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const: 0
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interrupts-extended:
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minItems: 1
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maxItems: 16384
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description:
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This property represents the set of CPUs (or HARTs) for which given
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device tree node describes the IMSIC interrupt files. Each node pointed
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to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V
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HART) as parent.
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riscv,num-ids:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 63
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maximum: 2047
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description:
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Number of interrupt identities supported by IMSIC interrupt file.
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riscv,num-guest-ids:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 63
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maximum: 2047
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description:
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Number of interrupt identities are supported by IMSIC guest interrupt
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file. When not specified it is assumed to be same as specified by the
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riscv,num-ids property.
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riscv,guest-index-bits:
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minimum: 0
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maximum: 7
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default: 0
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description:
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Number of guest index bits in the MSI target address.
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riscv,hart-index-bits:
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minimum: 0
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maximum: 15
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description:
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Number of HART index bits in the MSI target address. When not
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specified it is calculated based on the interrupts-extended property.
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riscv,group-index-bits:
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minimum: 0
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maximum: 7
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default: 0
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description:
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Number of group index bits in the MSI target address.
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riscv,group-index-shift:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 55
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default: 24
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description:
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The least significant bit position of the group index bits in the
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MSI target address.
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required:
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- compatible
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- reg
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- interrupt-controller
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- msi-controller
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- "#msi-cells"
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- interrupts-extended
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- riscv,num-ids
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unevaluatedProperties: false
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examples:
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- |
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// Example 1 (Machine-level IMSIC files with just one group):
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interrupt-controller@24000000 {
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compatible = "qemu,imsics", "riscv,imsics";
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interrupts-extended = <&cpu1_intc 11>,
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<&cpu2_intc 11>,
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<&cpu3_intc 11>,
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<&cpu4_intc 11>;
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reg = <0x28000000 0x4000>;
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interrupt-controller;
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#interrupt-cells = <0>;
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msi-controller;
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#msi-cells = <0>;
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riscv,num-ids = <127>;
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};
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- |
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// Example 2 (Supervisor-level IMSIC files with two groups):
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interrupt-controller@28000000 {
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compatible = "qemu,imsics", "riscv,imsics";
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interrupts-extended = <&cpu1_intc 9>,
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<&cpu2_intc 9>,
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<&cpu3_intc 9>,
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<&cpu4_intc 9>;
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reg = <0x28000000 0x2000>, /* Group0 IMSICs */
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<0x29000000 0x2000>; /* Group1 IMSICs */
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interrupt-controller;
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#interrupt-cells = <0>;
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msi-controller;
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#msi-cells = <0>;
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riscv,num-ids = <127>;
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riscv,group-index-bits = <1>;
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riscv,group-index-shift = <24>;
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};
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...

‎Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml

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reg = <0x5000d000 0x400>;
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};
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- |
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//Example 2
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exti2: interrupt-controller@40013c00 {
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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exti2: interrupt-controller@5000d000 {
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compatible = "st,stm32mp1-exti", "syscon";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000d000 0x400>;
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interrupts-extended =
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<&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<0>,
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<&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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- |
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//Example 3
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exti3: interrupt-controller@40013c00 {
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compatible = "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <2>;

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