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dt-bindings: clock: renesas: Document RZ/V2L SoC
Document the device tree binding for the Renesas RZ/V2L SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220110134659.30424-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

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$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode
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title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description: |
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On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
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On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
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Standby Mode share the same register block.
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They provide the following functionalities:
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properties:
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compatible:
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const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
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enum:
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- renesas,r9a07g044-cpg # RZ/G2{L,LC}
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- renesas,r9a07g054-cpg # RZ/V2L
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reg:
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maxItems: 1
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description: |
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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and a core clock reference, as defined in
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<dt-bindings/clock/r9a07g044-cpg.h>
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<dt-bindings/clock/r9a07g*-cpg.h>
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- For module clocks, the two clock specifier cells must be "CPG_MOD" and
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a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
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a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
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const: 2
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'#power-domain-cells':
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'#reset-cells':
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description:
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The single reset specifier cell must be the module number, as defined in
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the <dt-bindings/clock/r9a07g044-cpg.h>.
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the <dt-bindings/clock/r9a07g0*-cpg.h>.
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const: 1
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required:

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