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fdefrancdavejiang
fdefranc
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cxl/events: Use a common struct for DRAM and General Media events
cxl_event_common was an unfortunate naming choice and caused confusion with the existing Common Event Record. Furthermore, its fields didn't map all the common information between DRAM and General Media Events. Remove cxl_event_common and introduce cxl_event_media_hdr to record common information between DRAM and General Media events. cxl_event_media_hdr, which is embedded in both cxl_event_gen_media and cxl_event_dram, leverages the commonalities between the two events to simplify their respective handling. Suggested-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Fabio M. De Francesco <fabio.m.de.francesco@linux.intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20240607144423.48681-1-fabio.m.de.francesco@linux.intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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-68
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4 files changed

+65
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‎drivers/cxl/core/mbox.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -875,7 +875,7 @@ void cxl_event_trace_record(const struct cxl_memdev *cxlmd,
875875
guard(rwsem_read)(&cxl_region_rwsem);
876876
guard(rwsem_read)(&cxl_dpa_rwsem);
877877

878-
dpa = le64_to_cpu(evt->common.phys_addr) & CXL_DPA_MASK;
878+
dpa = le64_to_cpu(evt->media_hdr.phys_addr) & CXL_DPA_MASK;
879879
cxlr = cxl_dpa_to_region(cxlmd, dpa);
880880
if (cxlr)
881881
hpa = cxl_trace_hpa(cxlr, cxlmd, dpa);

‎drivers/cxl/core/trace.h

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -340,23 +340,23 @@ TRACE_EVENT(cxl_general_media,
340340
),
341341

342342
TP_fast_assign(
343-
CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr);
343+
CXL_EVT_TP_fast_assign(cxlmd, log, rec->media_hdr.hdr);
344344
__entry->hdr_uuid = CXL_EVENT_GEN_MEDIA_UUID;
345345

346346
/* General Media */
347-
__entry->dpa = le64_to_cpu(rec->phys_addr);
347+
__entry->dpa = le64_to_cpu(rec->media_hdr.phys_addr);
348348
__entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK;
349349
/* Mask after flags have been parsed */
350350
__entry->dpa &= CXL_DPA_MASK;
351-
__entry->descriptor = rec->descriptor;
352-
__entry->type = rec->type;
353-
__entry->transaction_type = rec->transaction_type;
354-
__entry->channel = rec->channel;
355-
__entry->rank = rec->rank;
351+
__entry->descriptor = rec->media_hdr.descriptor;
352+
__entry->type = rec->media_hdr.type;
353+
__entry->transaction_type = rec->media_hdr.transaction_type;
354+
__entry->channel = rec->media_hdr.channel;
355+
__entry->rank = rec->media_hdr.rank;
356356
__entry->device = get_unaligned_le24(rec->device);
357357
memcpy(__entry->comp_id, &rec->component_id,
358358
CXL_EVENT_GEN_MED_COMP_ID_SIZE);
359-
__entry->validity_flags = get_unaligned_le16(&rec->validity_flags);
359+
__entry->validity_flags = get_unaligned_le16(&rec->media_hdr.validity_flags);
360360
__entry->hpa = hpa;
361361
if (cxlr) {
362362
__assign_str(region_name);
@@ -440,19 +440,19 @@ TRACE_EVENT(cxl_dram,
440440
),
441441

442442
TP_fast_assign(
443-
CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr);
443+
CXL_EVT_TP_fast_assign(cxlmd, log, rec->media_hdr.hdr);
444444
__entry->hdr_uuid = CXL_EVENT_DRAM_UUID;
445445

446446
/* DRAM */
447-
__entry->dpa = le64_to_cpu(rec->phys_addr);
447+
__entry->dpa = le64_to_cpu(rec->media_hdr.phys_addr);
448448
__entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK;
449449
__entry->dpa &= CXL_DPA_MASK;
450-
__entry->descriptor = rec->descriptor;
451-
__entry->type = rec->type;
452-
__entry->transaction_type = rec->transaction_type;
453-
__entry->validity_flags = get_unaligned_le16(rec->validity_flags);
454-
__entry->channel = rec->channel;
455-
__entry->rank = rec->rank;
450+
__entry->descriptor = rec->media_hdr.descriptor;
451+
__entry->type = rec->media_hdr.type;
452+
__entry->transaction_type = rec->media_hdr.transaction_type;
453+
__entry->validity_flags = get_unaligned_le16(rec->media_hdr.validity_flags);
454+
__entry->channel = rec->media_hdr.channel;
455+
__entry->rank = rec->media_hdr.rank;
456456
__entry->nibble_mask = get_unaligned_le24(rec->nibble_mask);
457457
__entry->bank_group = rec->bank_group;
458458
__entry->bank = rec->bank;

‎include/linux/cxl-event.h

Lines changed: 19 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,21 @@ struct cxl_event_record_hdr {
2121
u8 reserved[15];
2222
} __packed;
2323

24+
struct cxl_event_media_hdr {
25+
struct cxl_event_record_hdr hdr;
26+
__le64 phys_addr;
27+
u8 descriptor;
28+
u8 type;
29+
u8 transaction_type;
30+
/*
31+
* The meaning of Validity Flags from bit 2 is
32+
* different across DRAM and General Media records
33+
*/
34+
u8 validity_flags[2];
35+
u8 channel;
36+
u8 rank;
37+
} __packed;
38+
2439
#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
2540
struct cxl_event_generic {
2641
struct cxl_event_record_hdr hdr;
@@ -33,14 +48,7 @@ struct cxl_event_generic {
3348
*/
3449
#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
3550
struct cxl_event_gen_media {
36-
struct cxl_event_record_hdr hdr;
37-
__le64 phys_addr;
38-
u8 descriptor;
39-
u8 type;
40-
u8 transaction_type;
41-
u8 validity_flags[2];
42-
u8 channel;
43-
u8 rank;
51+
struct cxl_event_media_hdr media_hdr;
4452
u8 device[3];
4553
u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
4654
u8 reserved[46];
@@ -52,14 +60,7 @@ struct cxl_event_gen_media {
5260
*/
5361
#define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20
5462
struct cxl_event_dram {
55-
struct cxl_event_record_hdr hdr;
56-
__le64 phys_addr;
57-
u8 descriptor;
58-
u8 type;
59-
u8 transaction_type;
60-
u8 validity_flags[2];
61-
u8 channel;
62-
u8 rank;
63+
struct cxl_event_media_hdr media_hdr;
6364
u8 nibble_mask[3];
6465
u8 bank_group;
6566
u8 bank;
@@ -95,21 +96,13 @@ struct cxl_event_mem_module {
9596
u8 reserved[0x3d];
9697
} __packed;
9798

98-
/*
99-
* General Media or DRAM Event Common Fields
100-
* - provides common access to phys_addr
101-
*/
102-
struct cxl_event_common {
103-
struct cxl_event_record_hdr hdr;
104-
__le64 phys_addr;
105-
} __packed;
106-
10799
union cxl_event {
108100
struct cxl_event_generic generic;
109101
struct cxl_event_gen_media gen_media;
110102
struct cxl_event_dram dram;
111103
struct cxl_event_mem_module mem_module;
112-
struct cxl_event_common common;
104+
/* dram & gen_media event header */
105+
struct cxl_event_media_hdr media_hdr;
113106
} __packed;
114107

115108
/*

‎tools/testing/cxl/test/mem.c

Lines changed: 29 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -385,19 +385,21 @@ struct cxl_test_gen_media {
385385
struct cxl_test_gen_media gen_media = {
386386
.id = CXL_EVENT_GEN_MEDIA_UUID,
387387
.rec = {
388-
.hdr = {
389-
.length = sizeof(struct cxl_test_gen_media),
390-
.flags[0] = CXL_EVENT_RECORD_FLAG_PERMANENT,
391-
/* .handle = Set dynamically */
392-
.related_handle = cpu_to_le16(0),
388+
.media_hdr = {
389+
.hdr = {
390+
.length = sizeof(struct cxl_test_gen_media),
391+
.flags[0] = CXL_EVENT_RECORD_FLAG_PERMANENT,
392+
/* .handle = Set dynamically */
393+
.related_handle = cpu_to_le16(0),
394+
},
395+
.phys_addr = cpu_to_le64(0x2000),
396+
.descriptor = CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT,
397+
.type = CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR,
398+
.transaction_type = CXL_GMER_TRANS_HOST_WRITE,
399+
/* .validity_flags = <set below> */
400+
.channel = 1,
401+
.rank = 30,
393402
},
394-
.phys_addr = cpu_to_le64(0x2000),
395-
.descriptor = CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT,
396-
.type = CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR,
397-
.transaction_type = CXL_GMER_TRANS_HOST_WRITE,
398-
/* .validity_flags = <set below> */
399-
.channel = 1,
400-
.rank = 30
401403
},
402404
};
403405

@@ -409,18 +411,20 @@ struct cxl_test_dram {
409411
struct cxl_test_dram dram = {
410412
.id = CXL_EVENT_DRAM_UUID,
411413
.rec = {
412-
.hdr = {
413-
.length = sizeof(struct cxl_test_dram),
414-
.flags[0] = CXL_EVENT_RECORD_FLAG_PERF_DEGRADED,
415-
/* .handle = Set dynamically */
416-
.related_handle = cpu_to_le16(0),
414+
.media_hdr = {
415+
.hdr = {
416+
.length = sizeof(struct cxl_test_dram),
417+
.flags[0] = CXL_EVENT_RECORD_FLAG_PERF_DEGRADED,
418+
/* .handle = Set dynamically */
419+
.related_handle = cpu_to_le16(0),
420+
},
421+
.phys_addr = cpu_to_le64(0x8000),
422+
.descriptor = CXL_GMER_EVT_DESC_THRESHOLD_EVENT,
423+
.type = CXL_GMER_MEM_EVT_TYPE_INV_ADDR,
424+
.transaction_type = CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB,
425+
/* .validity_flags = <set below> */
426+
.channel = 1,
417427
},
418-
.phys_addr = cpu_to_le64(0x8000),
419-
.descriptor = CXL_GMER_EVT_DESC_THRESHOLD_EVENT,
420-
.type = CXL_GMER_MEM_EVT_TYPE_INV_ADDR,
421-
.transaction_type = CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB,
422-
/* .validity_flags = <set below> */
423-
.channel = 1,
424428
.bank_group = 5,
425429
.bank = 2,
426430
.column = {0xDE, 0xAD},
@@ -474,11 +478,11 @@ static int mock_set_timestamp(struct cxl_dev_state *cxlds,
474478
static void cxl_mock_add_event_logs(struct mock_event_store *mes)
475479
{
476480
put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK,
477-
&gen_media.rec.validity_flags);
481+
&gen_media.rec.media_hdr.validity_flags);
478482

479483
put_unaligned_le16(CXL_DER_VALID_CHANNEL | CXL_DER_VALID_BANK_GROUP |
480484
CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN,
481-
&dram.rec.validity_flags);
485+
&dram.rec.media_hdr.validity_flags);
482486

483487
mes_add_event(mes, CXL_EVENT_TYPE_INFO, &maint_needed);
484488
mes_add_event(mes, CXL_EVENT_TYPE_INFO,

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