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Sam Protsenkokrzk
Sam Protsenko
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krzk
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clk: samsung: Don't pass reg_base to samsung_clk_register_pll()
Base address can be derived from context structure. Remove `base' argument from samsung_clk_register_pll() and use `ctx->reg_base' instead, as it's done in other clock registering functions. No functional change. Acked-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230223041938.22732-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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9 files changed

+16
-20
lines changed

9 files changed

+16
-20
lines changed

‎drivers/clk/samsung/clk-exynos4.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1276,7 +1276,7 @@ static void __init exynos4_clk_init(struct device_node *np,
12761276
exynos4210_vpll_rates;
12771277

12781278
samsung_clk_register_pll(ctx, exynos4210_plls,
1279-
ARRAY_SIZE(exynos4210_plls), reg_base);
1279+
ARRAY_SIZE(exynos4210_plls));
12801280
} else {
12811281
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
12821282
exynos4x12_plls[apll].rate_table =
@@ -1288,7 +1288,7 @@ static void __init exynos4_clk_init(struct device_node *np,
12881288
}
12891289

12901290
samsung_clk_register_pll(ctx, exynos4x12_plls,
1291-
ARRAY_SIZE(exynos4x12_plls), reg_base);
1291+
ARRAY_SIZE(exynos4x12_plls));
12921292
}
12931293

12941294
samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,

‎drivers/clk/samsung/clk-exynos5250.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -815,8 +815,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
815815
exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
816816

817817
samsung_clk_register_pll(ctx, exynos5250_plls,
818-
ARRAY_SIZE(exynos5250_plls),
819-
reg_base);
818+
ARRAY_SIZE(exynos5250_plls));
820819
samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
821820
ARRAY_SIZE(exynos5250_fixed_rate_clks));
822821
samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,

‎drivers/clk/samsung/clk-exynos5420.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1606,8 +1606,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
16061606
else
16071607
exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
16081608

1609-
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1610-
reg_base);
1609+
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls));
16111610
samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
16121611
ARRAY_SIZE(exynos5x_fixed_rate_clks));
16131612
samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,

‎drivers/clk/samsung/clk-exynos5433.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5610,8 +5610,8 @@ static int __init exynos5433_cmu_probe(struct platform_device *pdev)
56105610
pm_runtime_enable(dev);
56115611

56125612
if (info->pll_clks)
5613-
samsung_clk_register_pll(ctx, info->pll_clks, info->nr_pll_clks,
5614-
reg_base);
5613+
samsung_clk_register_pll(ctx, info->pll_clks,
5614+
info->nr_pll_clks);
56155615
if (info->mux_clks)
56165616
samsung_clk_register_mux(ctx, info->mux_clks,
56175617
info->nr_mux_clks);

‎drivers/clk/samsung/clk-pll.c

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1259,8 +1259,7 @@ static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
12591259
};
12601260

12611261
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
1262-
const struct samsung_pll_clock *pll_clk,
1263-
void __iomem *base)
1262+
const struct samsung_pll_clock *pll_clk)
12641263
{
12651264
struct samsung_clk_pll *pll;
12661265
struct clk_init_data init;
@@ -1395,8 +1394,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
13951394

13961395
pll->hw.init = &init;
13971396
pll->type = pll_clk->type;
1398-
pll->lock_reg = base + pll_clk->lock_offset;
1399-
pll->con_reg = base + pll_clk->con_offset;
1397+
pll->lock_reg = ctx->reg_base + pll_clk->lock_offset;
1398+
pll->con_reg = ctx->reg_base + pll_clk->con_offset;
14001399

14011400
ret = clk_hw_register(ctx->dev, &pll->hw);
14021401
if (ret) {
@@ -1412,10 +1411,10 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
14121411

14131412
void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
14141413
const struct samsung_pll_clock *pll_list,
1415-
unsigned int nr_pll, void __iomem *base)
1414+
unsigned int nr_pll)
14161415
{
14171416
int cnt;
14181417

14191418
for (cnt = 0; cnt < nr_pll; cnt++)
1420-
_samsung_clk_register_pll(ctx, &pll_list[cnt], base);
1419+
_samsung_clk_register_pll(ctx, &pll_list[cnt]);
14211420
}

‎drivers/clk/samsung/clk-s3c64xx.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -414,7 +414,7 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
414414

415415
/* Register PLLs. */
416416
samsung_clk_register_pll(ctx, s3c64xx_pll_clks,
417-
ARRAY_SIZE(s3c64xx_pll_clks), reg_base);
417+
ARRAY_SIZE(s3c64xx_pll_clks));
418418

419419
/* Register common internal clocks. */
420420
samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks,

‎drivers/clk/samsung/clk-s5pv210.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -753,7 +753,7 @@ static void __init __s5pv210_clk_init(struct device_node *np,
753753
samsung_clk_register_fixed_rate(ctx, s5p6442_frate_clks,
754754
ARRAY_SIZE(s5p6442_frate_clks));
755755
samsung_clk_register_pll(ctx, s5p6442_pll_clks,
756-
ARRAY_SIZE(s5p6442_pll_clks), reg_base);
756+
ARRAY_SIZE(s5p6442_pll_clks));
757757
samsung_clk_register_mux(ctx, s5p6442_mux_clks,
758758
ARRAY_SIZE(s5p6442_mux_clks));
759759
samsung_clk_register_div(ctx, s5p6442_div_clks,
@@ -764,7 +764,7 @@ static void __init __s5pv210_clk_init(struct device_node *np,
764764
samsung_clk_register_fixed_rate(ctx, s5pv210_frate_clks,
765765
ARRAY_SIZE(s5pv210_frate_clks));
766766
samsung_clk_register_pll(ctx, s5pv210_pll_clks,
767-
ARRAY_SIZE(s5pv210_pll_clks), reg_base);
767+
ARRAY_SIZE(s5pv210_pll_clks));
768768
samsung_clk_register_mux(ctx, s5pv210_mux_clks,
769769
ARRAY_SIZE(s5pv210_mux_clks));
770770
samsung_clk_register_div(ctx, s5pv210_div_clks,

‎drivers/clk/samsung/clk.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -344,8 +344,7 @@ struct samsung_clk_provider * __init samsung_cmu_register_one(
344344
ctx = samsung_clk_init(reg_base, cmu->nr_clk_ids);
345345

346346
if (cmu->pll_clks)
347-
samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
348-
reg_base);
347+
samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks);
349348
if (cmu->mux_clks)
350349
samsung_clk_register_mux(ctx, cmu->mux_clks,
351350
cmu->nr_mux_clks);

‎drivers/clk/samsung/clk.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -372,7 +372,7 @@ void samsung_clk_register_gate(struct samsung_clk_provider *ctx,
372372
unsigned int nr_clk);
373373
void samsung_clk_register_pll(struct samsung_clk_provider *ctx,
374374
const struct samsung_pll_clock *pll_list,
375-
unsigned int nr_clk, void __iomem *base);
375+
unsigned int nr_clk);
376376
void samsung_clk_register_cpu(struct samsung_clk_provider *ctx,
377377
const struct samsung_cpu_clock *list, unsigned int nr_clk);
378378

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