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clk: samsung: exynosautov9: add fsys1 clock support
CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL source clock provider. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/d4aa967538fed9667e9550a256e545026fc2fa8d.1659054220.git.chanho61.park@samsung.com
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‎drivers/clk/samsung/clk-exynosautov9.c

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Original file line numberDiff line numberDiff line change
@@ -1307,6 +1307,133 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
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.clk_name = "dout_clkcmu_fsys0_bus",
13081308
};
13091309

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/* ---- CMU_FSYS1 ---------------------------------------------------------- */
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/* Register Offset definitions for CMU_FSYS1 (0x17040000) */
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#define PLL_LOCKTIME_PLL_MMC 0x0000
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#define PLL_CON0_PLL_MMC 0x0100
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#define PLL_CON3_PLL_MMC 0x010c
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#define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600
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#define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610
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#define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620
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#define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000
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#define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800
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#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018
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#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c
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#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028
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#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c
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#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058
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#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064
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#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070
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#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074
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#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078
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#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c
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#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080
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static const unsigned long fsys1_clk_regs[] __initconst = {
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PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER,
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};
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static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = {
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PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
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PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
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};
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/* List of parent clocks for Muxes in CMU_FSYS1 */
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PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_clkcmu_fsys1_bus" };
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PNAME(mout_fsys1_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
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PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk", "gout_clkcmu_fsys1_mmc_card" };
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PNAME(mout_fsys1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_fsys1_usbdrd" };
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PNAME(mout_fsys1_mmc_card_p) = { "mout_fsys1_mmc_card_user",
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"mout_fsys1_mmc_pll" };
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static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
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MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
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mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1),
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MUX(CLK_MOUT_FSYS1_MMC_PLL, "mout_fsys1_mmc_pll", mout_fsys1_mmc_pll_p,
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PLL_CON0_PLL_MMC, 4, 1),
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MUX(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user",
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mout_fsys1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
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4, 1),
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MUX(CLK_MOUT_FSYS1_USBDRD_USER, "mout_fsys1_usbdrd_user",
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mout_fsys1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER,
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4, 1),
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MUX(CLK_MOUT_FSYS1_MMC_CARD, "mout_fsys1_mmc_card",
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mout_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD,
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0, 1),
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};
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static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
1371+
DIV(CLK_DOUT_FSYS1_MMC_CARD, "dout_fsys1_mmc_card",
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"mout_fsys1_mmc_card",
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CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
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};
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static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
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GATE(CLK_GOUT_FSYS1_PCLK, "gout_fsys1_pclk", "mout_fsys1_bus_user",
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CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
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21, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin",
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"dout_fsys1_mmc_card",
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CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
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21, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_GOUT_FSYS1_MMC_CARD_ACLK, "gout_fsys1_mmc_card_aclk",
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"dout_fsys1_mmc_card",
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CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
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21, 0, 0),
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GATE(CLK_GOUT_FSYS1_USB20DRD_0_REFCLK, "gout_fsys1_usb20drd_0_refclk",
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"mout_fsys1_usbdrd_user",
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CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40,
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21, 0, 0),
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GATE(CLK_GOUT_FSYS1_USB20DRD_1_REFCLK, "gout_fsys1_usb20drd_1_refclk",
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"mout_fsys1_usbdrd_user",
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CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40,
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21, 0, 0),
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GATE(CLK_GOUT_FSYS1_USB30DRD_0_REFCLK, "gout_fsys1_usb30drd_0_refclk",
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"mout_fsys1_usbdrd_user",
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CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40,
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21, 0, 0),
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GATE(CLK_GOUT_FSYS1_USB30DRD_1_REFCLK, "gout_fsys1_usb30drd_1_refclk",
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"mout_fsys1_usbdrd_user",
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CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40,
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21, 0, 0),
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GATE(CLK_GOUT_FSYS1_USB20_0_ACLK, "gout_fsys1_usb20_0_aclk",
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"mout_fsys1_usbdrd_user",
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CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK,
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21, 0, 0),
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GATE(CLK_GOUT_FSYS1_USB20_1_ACLK, "gout_fsys1_usb20_1_aclk",
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"mout_fsys1_usbdrd_user",
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CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK,
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21, 0, 0),
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GATE(CLK_GOUT_FSYS1_USB30_0_ACLK, "gout_fsys1_usb30_0_aclk",
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"mout_fsys1_usbdrd_user",
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CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK,
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21, 0, 0),
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GATE(CLK_GOUT_FSYS1_USB30_1_ACLK, "gout_fsys1_usb30_1_aclk",
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"mout_fsys1_usbdrd_user",
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CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK,
1419+
21, 0, 0),
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};
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static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
1423+
.pll_clks = fsys1_pll_clks,
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.nr_pll_clks = ARRAY_SIZE(fsys1_pll_clks),
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.mux_clks = fsys1_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
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.div_clks = fsys1_div_clks,
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.nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
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.gate_clks = fsys1_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
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.nr_clk_ids = FSYS1_NR_CLK,
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.clk_regs = fsys1_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
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.clk_name = "dout_clkcmu_fsys1_bus",
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};
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13101437
/* ---- CMU_FSYS2 ---------------------------------------------------------- */
13111438

13121439
/* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
@@ -1952,6 +2079,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
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}, {
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.compatible = "samsung,exynosautov9-cmu-fsys0",
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.data = &fsys0_cmu_info,
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}, {
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.compatible = "samsung,exynosautov9-cmu-fsys1",
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.data = &fsys1_cmu_info,
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}, {
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.compatible = "samsung,exynosautov9-cmu-fsys2",
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.data = &fsys2_cmu_info,

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