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Merge tag 'v6.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
Basic graphics support for rv1126, some more new peripherals for it as well and some improvements for the edgeble-neu2 board based on this soc. * tag 'v6.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: Add rv1126 VOP_LITE support ARM: dts: rockchip: Add rv1126 PD_VO entry ARM: dts: rockchip: Add 12V main supply for edgeble-neu2 ARM: dts: rockchip: Add 3V3_SYS regulator for edgeble-neu2 ARM: dts: rockchip: Enable SFC for edgeble-neu2 ARM: dts: rockchip: Drop EMMC_RSTN for edgeble-neu2 ARM: dts: rockchip: Add rv1126 uart5m2_xfer pins ARM: dts: rockchip: Add rv1126 FSPI pins ARM: dts: rockchip: Add SFC node to rv1126 Link: https://lore.kernel.org/r/6299163.hdfAi7Kttb@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents b89c940 + 1bf0dcb commit 5948696

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4 files changed

+165
-10
lines changed

4 files changed

+165
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lines changed

‎arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,35 @@
2020
chosen {
2121
stdout-path = "serial2:1500000n8";
2222
};
23+
24+
vcc12v_dcin: vcc12v-dcin-regulator {
25+
compatible = "regulator-fixed";
26+
regulator-name = "vcc12v_dcin";
27+
regulator-always-on;
28+
regulator-boot-on;
29+
regulator-min-microvolt = <12000000>;
30+
regulator-max-microvolt = <12000000>;
31+
};
32+
33+
vcc5v0_sys: vcc5v0-sys-regulator {
34+
compatible = "regulator-fixed";
35+
regulator-name = "vcc5v0_sys";
36+
regulator-always-on;
37+
regulator-boot-on;
38+
regulator-min-microvolt = <5000000>;
39+
regulator-max-microvolt = <5000000>;
40+
vin-supply = <&vcc12v_dcin>;
41+
};
42+
43+
v3v3_sys: v3v3-sys-regulator {
44+
compatible = "regulator-fixed";
45+
regulator-name = "v3v3_sys";
46+
regulator-always-on;
47+
regulator-boot-on;
48+
regulator-min-microvolt = <3300000>;
49+
regulator-max-microvolt = <3300000>;
50+
vin-supply = <&vcc5v0_sys>;
51+
};
2352
};
2453

2554
&gmac {

‎arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi

Lines changed: 17 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -11,15 +11,6 @@
1111
mmc0 = &emmc;
1212
};
1313

14-
vcc5v0_sys: vcc5v0-sys-regulator {
15-
compatible = "regulator-fixed";
16-
regulator-name = "vcc5v0_sys";
17-
regulator-always-on;
18-
regulator-boot-on;
19-
regulator-min-microvolt = <5000000>;
20-
regulator-max-microvolt = <5000000>;
21-
};
22-
2314
vccio_flash: vccio-flash-regulator {
2415
compatible = "regulator-fixed";
2516
enable-active-high;
@@ -52,7 +43,7 @@
5243
bus-width = <8>;
5344
non-removable;
5445
pinctrl-names = "default";
55-
pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
46+
pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>;
5647
rockchip,default-sample-phase = <90>;
5748
vmmc-supply = <&vcc_3v3>;
5849
vqmmc-supply = <&vccio_flash>;
@@ -301,6 +292,22 @@
301292
status = "okay";
302293
};
303294

295+
&sfc {
296+
pinctrl-names = "default";
297+
pinctrl-0 = <&fspi_pins>;
298+
#address-cells = <1>;
299+
#size-cells = <0>;
300+
status = "okay";
301+
302+
flash@0 {
303+
compatible = "jedec,spi-nor";
304+
reg = <0>;
305+
spi-max-frequency = <50000000>;
306+
spi-rx-bus-width = <4>;
307+
spi-tx-bus-width = <1>;
308+
};
309+
};
310+
304311
&sdio {
305312
bus-width = <4>;
306313
cap-sd-highspeed;

‎arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,24 @@
5959
<0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
6060
};
6161
};
62+
fspi {
63+
/omit-if-no-ref/
64+
fspi_pins: fspi-pins {
65+
rockchip,pins =
66+
/* fspi_clk */
67+
<1 RK_PA3 3 &pcfg_pull_down>,
68+
/* fspi_cs0n */
69+
<0 RK_PD4 3 &pcfg_pull_up>,
70+
/* fspi_d0 */
71+
<1 RK_PA0 3 &pcfg_pull_up>,
72+
/* fspi_d1 */
73+
<1 RK_PA1 3 &pcfg_pull_up>,
74+
/* fspi_d2 */
75+
<0 RK_PD6 3 &pcfg_pull_up>,
76+
/* fspi_d3 */
77+
<1 RK_PA2 3 &pcfg_pull_up>;
78+
};
79+
};
6280
i2c0 {
6381
/omit-if-no-ref/
6482
i2c0_xfer: i2c0-xfer {
@@ -249,5 +267,13 @@
249267
/* uart5_tx_m0 */
250268
<3 RK_PA6 4 &pcfg_pull_up>;
251269
};
270+
/omit-if-no-ref/
271+
uart5m2_xfer: uart5m2-xfer {
272+
rockchip,pins =
273+
/* uart5_rx_m2 */
274+
<2 RK_PA1 3 &pcfg_pull_up>,
275+
/* uart5_tx_m2 */
276+
<2 RK_PA0 3 &pcfg_pull_up>;
277+
};
252278
};
253279
};

‎arch/arm/boot/dts/rockchip/rv1126.dtsi

Lines changed: 93 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,11 @@
8383
clock-frequency = <24000000>;
8484
};
8585

86+
display_subsystem {
87+
compatible = "rockchip,display-subsystem";
88+
ports = <&vop_out>;
89+
};
90+
8691
xin24m: oscillator {
8792
compatible = "fixed-clock";
8893
clock-frequency = <24000000>;
@@ -125,6 +130,26 @@
125130
reg = <0xfe86c000 0x20>;
126131
};
127132

133+
qos_iep: qos@fe8a0000 {
134+
compatible = "rockchip,rv1126-qos", "syscon";
135+
reg = <0xfe8a0000 0x20>;
136+
};
137+
138+
qos_rga_rd: qos@fe8a0080 {
139+
compatible = "rockchip,rv1126-qos", "syscon";
140+
reg = <0xfe8a0080 0x20>;
141+
};
142+
143+
qos_rga_wr: qos@fe8a0100 {
144+
compatible = "rockchip,rv1126-qos", "syscon";
145+
reg = <0xfe8a0100 0x20>;
146+
};
147+
148+
qos_vop: qos@fe8a0180 {
149+
compatible = "rockchip,rv1126-qos", "syscon";
150+
reg = <0xfe8a0180 0x20>;
151+
};
152+
128153
gic: interrupt-controller@feff0000 {
129154
compatible = "arm,gic-400";
130155
interrupt-controller;
@@ -170,6 +195,25 @@
170195
pm_qos = <&qos_sdio>;
171196
#power-domain-cells = <0>;
172197
};
198+
199+
power-domain@RV1126_PD_VO {
200+
reg = <RV1126_PD_VO>;
201+
clocks = <&cru ACLK_RGA>,
202+
<&cru HCLK_RGA>,
203+
<&cru CLK_RGA_CORE>,
204+
<&cru ACLK_VOP>,
205+
<&cru HCLK_VOP>,
206+
<&cru DCLK_VOP>,
207+
<&cru PCLK_DSIHOST>,
208+
<&cru ACLK_IEP>,
209+
<&cru HCLK_IEP>,
210+
<&cru CLK_IEP_CORE>;
211+
pm_qos = <&qos_rga_rd>,
212+
<&qos_rga_wr>,
213+
<&qos_vop>,
214+
<&qos_iep>;
215+
#power-domain-cells = <0>;
216+
};
173217
};
174218
};
175219

@@ -332,6 +376,43 @@
332376
clock-names = "pclk", "timer";
333377
};
334378

379+
vop: vop@ffb00000 {
380+
compatible = "rockchip,rv1126-vop";
381+
reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
382+
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
383+
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
384+
clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
385+
reset-names = "axi", "ahb", "dclk";
386+
resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
387+
iommus = <&vop_mmu>;
388+
power-domains = <&power RV1126_PD_VO>;
389+
status = "disabled";
390+
391+
vop_out: port {
392+
#address-cells = <1>;
393+
#size-cells = <0>;
394+
395+
vop_out_rgb: endpoint@0 {
396+
reg = <0>;
397+
};
398+
399+
vop_out_dsi: endpoint@1 {
400+
reg = <1>;
401+
};
402+
};
403+
};
404+
405+
vop_mmu: iommu@ffb00f00 {
406+
compatible = "rockchip,iommu";
407+
reg = <0xffb00f00 0x100>;
408+
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
409+
clock-names = "aclk", "iface";
410+
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
411+
#iommu-cells = <0>;
412+
power-domains = <&power RV1126_PD_VO>;
413+
status = "disabled";
414+
};
415+
335416
gmac: ethernet@ffc40000 {
336417
compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
337418
reg = <0xffc40000 0x4000>;
@@ -419,6 +500,18 @@
419500
status = "disabled";
420501
};
421502

503+
sfc: spi@ffc90000 {
504+
compatible = "rockchip,sfc";
505+
reg = <0xffc90000 0x4000>;
506+
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
507+
assigned-clocks = <&cru SCLK_SFC>;
508+
assigned-clock-rates = <80000000>;
509+
clock-names = "clk_sfc", "hclk_sfc";
510+
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
511+
power-domains = <&power RV1126_PD_NVM>;
512+
status = "disabled";
513+
};
514+
422515
pinctrl: pinctrl {
423516
compatible = "rockchip,rv1126-pinctrl";
424517
rockchip,grf = <&grf>;

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