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Wojciech DubowikShawn Guo
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arm64: dts: imx8mm-verdin: Link reg_usdhc2_vqmmc to usdhc2
Define vqmmc regulator-gpio for usdhc2 with vin-supply coming from LDO5. Without this definition LDO5 will be powered down, disabling SD card after bootup. This has been introduced in commit f5aab04 ("regulator: pca9450: Fix enable register for LDO5"). Fixes: 6a57f22 ("arm64: dts: freescale: add initial support for verdin imx8m mini") Fixes: f5aab04 ("regulator: pca9450: Fix enable register for LDO5") Tested-by: Manuel Traut <manuel.traut@mt.com> Reviewed-by: Philippe Schenker <philippe.schenker@impulsing.ch> Tested-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Cc: stable@vger.kernel.org Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@mt.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi

Lines changed: 20 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,19 @@
144144
startup-delay-us = <20000>;
145145
};
146146

147+
reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
148+
compatible = "regulator-gpio";
149+
pinctrl-names = "default";
150+
pinctrl-0 = <&pinctrl_usdhc2_vsel>;
151+
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
152+
regulator-max-microvolt = <3300000>;
153+
regulator-min-microvolt = <1800000>;
154+
states = <1800000 0x1>,
155+
<3300000 0x0>;
156+
regulator-name = "PMIC_USDHC_VSELECT";
157+
vin-supply = <&reg_nvcc_sd>;
158+
};
159+
147160
reserved-memory {
148161
#address-cells = <2>;
149162
#size-cells = <2>;
@@ -269,7 +282,7 @@
269282
"SODIMM_19",
270283
"",
271284
"",
272-
"",
285+
"PMIC_USDHC_VSELECT",
273286
"",
274287
"",
275288
"",
@@ -785,6 +798,7 @@
785798
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
786799
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
787800
vmmc-supply = <&reg_usdhc2_vmmc>;
801+
vqmmc-supply = <&reg_usdhc2_vqmmc>;
788802
};
789803

790804
&wdog1 {
@@ -1206,13 +1220,17 @@
12061220
<MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
12071221
};
12081222

1223+
pinctrl_usdhc2_vsel: usdhc2vselgrp {
1224+
fsl,pins =
1225+
<MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x10>; /* PMIC_USDHC_VSELECT */
1226+
};
1227+
12091228
/*
12101229
* Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
12111230
* on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
12121231
*/
12131232
pinctrl_usdhc2: usdhc2grp {
12141233
fsl,pins =
1215-
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
12161234
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
12171235
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
12181236
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
@@ -1223,7 +1241,6 @@
12231241

12241242
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
12251243
fsl,pins =
1226-
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
12271244
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
12281245
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
12291246
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
@@ -1234,7 +1251,6 @@
12341251

12351252
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
12361253
fsl,pins =
1237-
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
12381254
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
12391255
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
12401256
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
@@ -1246,7 +1262,6 @@
12461262
/* Avoid backfeeding with removed card power */
12471263
pinctrl_usdhc2_sleep: usdhc2slpgrp {
12481264
fsl,pins =
1249-
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>,
12501265
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
12511266
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
12521267
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,

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