|
144 | 144 | startup-delay-us = <20000>;
|
145 | 145 | };
|
146 | 146 |
|
| 147 | + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { |
| 148 | + compatible = "regulator-gpio"; |
| 149 | + pinctrl-names = "default"; |
| 150 | + pinctrl-0 = <&pinctrl_usdhc2_vsel>; |
| 151 | + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; |
| 152 | + regulator-max-microvolt = <3300000>; |
| 153 | + regulator-min-microvolt = <1800000>; |
| 154 | + states = <1800000 0x1>, |
| 155 | + <3300000 0x0>; |
| 156 | + regulator-name = "PMIC_USDHC_VSELECT"; |
| 157 | + vin-supply = <®_nvcc_sd>; |
| 158 | + }; |
| 159 | + |
147 | 160 | reserved-memory {
|
148 | 161 | #address-cells = <2>;
|
149 | 162 | #size-cells = <2>;
|
|
269 | 282 | "SODIMM_19",
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270 | 283 | "",
|
271 | 284 | "",
|
272 |
| - "", |
| 285 | + "PMIC_USDHC_VSELECT", |
273 | 286 | "",
|
274 | 287 | "",
|
275 | 288 | "",
|
|
785 | 798 | pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
|
786 | 799 | pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
|
787 | 800 | vmmc-supply = <®_usdhc2_vmmc>;
|
| 801 | + vqmmc-supply = <®_usdhc2_vqmmc>; |
788 | 802 | };
|
789 | 803 |
|
790 | 804 | &wdog1 {
|
|
1206 | 1220 | <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
|
1207 | 1221 | };
|
1208 | 1222 |
|
| 1223 | + pinctrl_usdhc2_vsel: usdhc2vselgrp { |
| 1224 | + fsl,pins = |
| 1225 | + <MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x10>; /* PMIC_USDHC_VSELECT */ |
| 1226 | + }; |
| 1227 | + |
1209 | 1228 | /*
|
1210 | 1229 | * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
|
1211 | 1230 | * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
|
1212 | 1231 | */
|
1213 | 1232 | pinctrl_usdhc2: usdhc2grp {
|
1214 | 1233 | fsl,pins =
|
1215 |
| - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, |
1216 | 1234 | <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
|
1217 | 1235 | <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
|
1218 | 1236 | <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
|
|
1223 | 1241 |
|
1224 | 1242 | pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
1225 | 1243 | fsl,pins =
|
1226 |
| - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, |
1227 | 1244 | <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
|
1228 | 1245 | <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
|
1229 | 1246 | <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
|
|
1234 | 1251 |
|
1235 | 1252 | pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
1236 | 1253 | fsl,pins =
|
1237 |
| - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, |
1238 | 1254 | <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
|
1239 | 1255 | <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
|
1240 | 1256 | <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
|
|
1246 | 1262 | /* Avoid backfeeding with removed card power */
|
1247 | 1263 | pinctrl_usdhc2_sleep: usdhc2slpgrp {
|
1248 | 1264 | fsl,pins =
|
1249 |
| - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>, |
1250 | 1265 | <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
|
1251 | 1266 | <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
|
1252 | 1267 | <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
|
|
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