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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Will Deacon: "I think we have a bit less than usual on the architecture side, but that's somewhat balanced out by a large crop of perf/PMU driver updates and extensions to our selftests. CPU features and system registers: - Advertise hinted conditional branch support (FEAT_HBC) to userspace - Avoid false positive "SANITY CHECK" warning when xCR registers differ outside of the length field Documentation: - Fix macro name typo in SME documentation Entry code: - Unmask exceptions earlier on the system call entry path Memory management: - Don't bother clearing PTE_RDONLY for dirty ptes in pte_wrprotect() and pte_modify() Perf and PMU drivers: - Initial support for Coresight TRBE devices on ACPI systems (the coresight driver changes will come later) - Fix hw_breakpoint single-stepping when called from bpf - Fixes for DDR PMU on i.MX8MP SoC - Add NUMA-awareness to Hisilicon PCIe PMU driver - Fix locking dependency issue in Arm DMC620 PMU driver - Workaround Hisilicon erratum 162001900 in the SMMUv3 PMU driver - Add support for Arm CMN-700 r3 parts to the CMN PMU driver - Add support for recent Arm Cortex CPU PMUs - Update Hisilicon PMU maintainers Selftests: - Add a bunch of new features to the hwcap test (JSCVT, PMULL, AES, SHA1, etc) - Fix SSVE test to leave streaming-mode after grabbing the signal context - Add new test for SVE vector-length changes with SME enabled Miscellaneous: - Allow compiler to warn on suspicious looking system register expressions - Work around SDEI firmware bug by aborting any running handlers on a kernel crash - Fix some harmless warnings when building with W=1 - Remove some unused function declarations - Other minor fixes and cleanup" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (62 commits) drivers/perf: hisi: Update HiSilicon PMU maintainers arm_pmu: acpi: Add a representative platform device for TRBE arm_pmu: acpi: Refactor arm_spe_acpi_register_device() kselftest/arm64: Fix hwcaps selftest build hw_breakpoint: fix single-stepping when using bpf_overflow_handler arm64/sysreg: refactor deprecated strncpy kselftest/arm64: add jscvt feature to hwcap test kselftest/arm64: add pmull feature to hwcap test kselftest/arm64: add AES feature check to hwcap test kselftest/arm64: add SHA1 and related features to hwcap test arm64: sysreg: Generate C compiler warnings on {read,write}_sysreg_s arguments kselftest/arm64: build BTI tests in output directory perf/imx_ddr: don't enable counter0 if none of 4 counters are used perf/imx_ddr: speed up overflow frequency of cycle drivers/perf: hisi: Schedule perf session according to locality kselftest/arm64: fix a memleak in zt_regs_run() perf/arm-dmc620: Fix dmc620_pmu_irqs_lock/cpu_hotplug_lock circular lock dependency perf/smmuv3: Add MODULE_ALIAS for module auto loading perf/smmuv3: Enable HiSilicon Erratum 162001900 quirk for HIP08/09 kselftest/arm64: Size sycall-abi buffers for the actual maximum VL ...
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‎Documentation/arch/arm64/silicon-errata.rst

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,14 @@ stable kernels.
6363
+----------------+-----------------+-----------------+-----------------------------+
6464
| ARM | Cortex-A510 | #1902691 | ARM64_ERRATUM_1902691 |
6565
+----------------+-----------------+-----------------+-----------------------------+
66+
| ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 |
67+
+----------------+-----------------+-----------------+-----------------------------+
68+
| ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 |
69+
+----------------+-----------------+-----------------+-----------------------------+
70+
| ARM | Cortex-A510 | #2441009 | ARM64_ERRATUM_2441009 |
71+
+----------------+-----------------+-----------------+-----------------------------+
72+
| ARM | Cortex-A510 | #2658417 | ARM64_ERRATUM_2658417 |
73+
+----------------+-----------------+-----------------+-----------------------------+
6674
| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
6775
+----------------+-----------------+-----------------+-----------------------------+
6876
| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
@@ -109,14 +117,6 @@ stable kernels.
109117
+----------------+-----------------+-----------------+-----------------------------+
110118
| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
111119
+----------------+-----------------+-----------------+-----------------------------+
112-
| ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 |
113-
+----------------+-----------------+-----------------+-----------------------------+
114-
| ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 |
115-
+----------------+-----------------+-----------------+-----------------------------+
116-
| ARM | Cortex-A510 | #2441009 | ARM64_ERRATUM_2441009 |
117-
+----------------+-----------------+-----------------+-----------------------------+
118-
| ARM | Cortex-A510 | #2658417 | ARM64_ERRATUM_2658417 |
119-
+----------------+-----------------+-----------------+-----------------------------+
120120
| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
121121
+----------------+-----------------+-----------------+-----------------------------+
122122
| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
@@ -198,6 +198,9 @@ stable kernels.
198198
+----------------+-----------------+-----------------+-----------------------------+
199199
| Hisilicon | Hip08 SMMU PMCG | #162001800 | N/A |
200200
+----------------+-----------------+-----------------+-----------------------------+
201+
| Hisilicon | Hip08 SMMU PMCG | #162001900 | N/A |
202+
| | Hip09 SMMU PMCG | | |
203+
+----------------+-----------------+-----------------+-----------------------------+
201204
+----------------+-----------------+-----------------+-----------------------------+
202205
| Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
203206
+----------------+-----------------+-----------------+-----------------------------+

‎Documentation/arch/arm64/sme.rst

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -322,7 +322,7 @@ The regset data starts with struct user_za_header, containing:
322322
VL is supported.
323323

324324
* The size and layout of the payload depends on the header fields. The
325-
SME_PT_ZA_*() macros are provided to facilitate access to the data.
325+
ZA_PT_ZA*() macros are provided to facilitate access to the data.
326326

327327
* In either case, for SETREGSET it is permissible to omit the payload, in which
328328
case the vector length and flags are changed and PSTATE.ZA is set to 0

‎Documentation/devicetree/bindings/arm/pmu.yaml

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Original file line numberDiff line numberDiff line change
@@ -49,9 +49,14 @@ properties:
4949
- arm,cortex-a77-pmu
5050
- arm,cortex-a78-pmu
5151
- arm,cortex-a510-pmu
52+
- arm,cortex-a520-pmu
5253
- arm,cortex-a710-pmu
54+
- arm,cortex-a715-pmu
55+
- arm,cortex-a720-pmu
5356
- arm,cortex-x1-pmu
5457
- arm,cortex-x2-pmu
58+
- arm,cortex-x3-pmu
59+
- arm,cortex-x4-pmu
5560
- arm,neoverse-e1-pmu
5661
- arm,neoverse-n1-pmu
5762
- arm,neoverse-n2-pmu

‎MAINTAINERS

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9306,7 +9306,7 @@ F: drivers/crypto/hisilicon/hpre/hpre_crypto.c
93069306
F: drivers/crypto/hisilicon/hpre/hpre_main.c
93079307

93089308
HISILICON HNS3 PMU DRIVER
9309-
M: Guangbin Huang <huangguangbin2@huawei.com>
9309+
M: Jijie Shao <shaojijie@huawei.com>
93109310
S: Supported
93119311
F: Documentation/admin-guide/perf/hns3-pmu.rst
93129312
F: drivers/perf/hisilicon/hns3_pmu.c
@@ -9344,7 +9344,7 @@ F: Documentation/devicetree/bindings/net/hisilicon*.txt
93449344
F: drivers/net/ethernet/hisilicon/
93459345

93469346
HISILICON PMU DRIVER
9347-
M: Shaokun Zhang <zhangshaokun@hisilicon.com>
9347+
M: Yicong Yang <yangyicong@hisilicon.com>
93489348
M: Jonathan Cameron <jonathan.cameron@huawei.com>
93499349
S: Supported
93509350
W: http://www.hisilicon.com

‎arch/arm/kernel/hw_breakpoint.c

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Original file line numberDiff line numberDiff line change
@@ -626,7 +626,7 @@ int hw_breakpoint_arch_parse(struct perf_event *bp,
626626
hw->address &= ~alignment_mask;
627627
hw->ctrl.len <<= offset;
628628

629-
if (is_default_overflow_handler(bp)) {
629+
if (uses_default_overflow_handler(bp)) {
630630
/*
631631
* Mismatch breakpoints are required for single-stepping
632632
* breakpoints.
@@ -798,7 +798,7 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr,
798798
* Otherwise, insert a temporary mismatch breakpoint so that
799799
* we can single-step over the watchpoint trigger.
800800
*/
801-
if (!is_default_overflow_handler(wp))
801+
if (!uses_default_overflow_handler(wp))
802802
continue;
803803
step:
804804
enable_single_step(wp, instruction_pointer(regs));
@@ -811,7 +811,7 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr,
811811
info->trigger = addr;
812812
pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
813813
perf_bp_event(wp, regs);
814-
if (is_default_overflow_handler(wp))
814+
if (uses_default_overflow_handler(wp))
815815
enable_single_step(wp, instruction_pointer(regs));
816816
}
817817

@@ -886,7 +886,7 @@ static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
886886
info->trigger = addr;
887887
pr_debug("breakpoint fired: address = 0x%x\n", addr);
888888
perf_bp_event(bp, regs);
889-
if (is_default_overflow_handler(bp))
889+
if (uses_default_overflow_handler(bp))
890890
enable_single_step(bp, addr);
891891
goto unlock;
892892
}

‎arch/arm64/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -1793,9 +1793,6 @@ config ARM64_PAN
17931793
The feature is detected at runtime, and will remain as a 'nop'
17941794
instruction if the cpu does not implement the feature.
17951795

1796-
config AS_HAS_LDAPR
1797-
def_bool $(as-instr,.arch_extension rcpc)
1798-
17991796
config AS_HAS_LSE_ATOMICS
18001797
def_bool $(as-instr,.arch_extension lse)
18011798

@@ -1933,6 +1930,9 @@ config AS_HAS_ARMV8_3
19331930
config AS_HAS_CFI_NEGATE_RA_STATE
19341931
def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
19351932

1933+
config AS_HAS_LDAPR
1934+
def_bool $(as-instr,.arch_extension rcpc)
1935+
19361936
endmenu # "ARMv8.3 architectural features"
19371937

19381938
menu "ARMv8.4 architectural features"

‎arch/arm64/include/asm/acpi.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,9 @@
4242
#define ACPI_MADT_GICC_SPE (offsetof(struct acpi_madt_generic_interrupt, \
4343
spe_interrupt) + sizeof(u16))
4444

45+
#define ACPI_MADT_GICC_TRBE (offsetof(struct acpi_madt_generic_interrupt, \
46+
trbe_interrupt) + sizeof(u16))
47+
4548
/* Basic configuration for ACPI */
4649
#ifdef CONFIG_ACPI
4750
pgprot_t __acpi_get_mem_attribute(phys_addr_t addr);

‎arch/arm64/include/asm/hwcap.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,7 @@
138138
#define KERNEL_HWCAP_SME_B16B16 __khwcap2_feature(SME_B16B16)
139139
#define KERNEL_HWCAP_SME_F16F16 __khwcap2_feature(SME_F16F16)
140140
#define KERNEL_HWCAP_MOPS __khwcap2_feature(MOPS)
141+
#define KERNEL_HWCAP_HBC __khwcap2_feature(HBC)
141142

142143
/*
143144
* This yields a mask that user programs can use to figure out what

‎arch/arm64/include/asm/kernel-pgtable.h

Lines changed: 0 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -118,31 +118,4 @@
118118
#define SWAPPER_RX_MMUFLAGS (SWAPPER_RW_MMUFLAGS | PTE_RDONLY)
119119
#endif
120120

121-
/*
122-
* To make optimal use of block mappings when laying out the linear
123-
* mapping, round down the base of physical memory to a size that can
124-
* be mapped efficiently, i.e., either PUD_SIZE (4k granule) or PMD_SIZE
125-
* (64k granule), or a multiple that can be mapped using contiguous bits
126-
* in the page tables: 32 * PMD_SIZE (16k granule)
127-
*/
128-
#if defined(CONFIG_ARM64_4K_PAGES)
129-
#define ARM64_MEMSTART_SHIFT PUD_SHIFT
130-
#elif defined(CONFIG_ARM64_16K_PAGES)
131-
#define ARM64_MEMSTART_SHIFT CONT_PMD_SHIFT
132-
#else
133-
#define ARM64_MEMSTART_SHIFT PMD_SHIFT
134-
#endif
135-
136-
/*
137-
* sparsemem vmemmap imposes an additional requirement on the alignment of
138-
* memstart_addr, due to the fact that the base of the vmemmap region
139-
* has a direct correspondence, and needs to appear sufficiently aligned
140-
* in the virtual address space.
141-
*/
142-
#if ARM64_MEMSTART_SHIFT < SECTION_SIZE_BITS
143-
#define ARM64_MEMSTART_ALIGN (1UL << SECTION_SIZE_BITS)
144-
#else
145-
#define ARM64_MEMSTART_ALIGN (1UL << ARM64_MEMSTART_SHIFT)
146-
#endif
147-
148121
#endif /* __ASM_KERNEL_PGTABLE_H */

‎arch/arm64/include/asm/mmu.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,6 @@ extern void arm64_memblock_init(void);
6464
extern void paging_init(void);
6565
extern void bootmem_init(void);
6666
extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
67-
extern void init_mem_pgprot(void);
6867
extern void create_mapping_noalloc(phys_addr_t phys, unsigned long virt,
6968
phys_addr_t size, pgprot_t prot);
7069
extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,

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