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Merge branch kvm-arm64/nv-trap-fixes into kvmarm/next
* kvm-arm64/nv-trap-fixes: : NV trap forwarding fixes, courtesy Miguel Luis and Marc Zyngier : : - Explicitly define the effects of HCR_EL2.NV on EL2 sysregs in the : NV trap encoding : : - Make EL2 registers that access AArch32 guest state UNDEF or RAZ/WI : where appropriate for NV guests KVM: arm64: Handle AArch32 SPSR_{irq,abt,und,fiq} as RAZ/WI KVM: arm64: Do not let a L1 hypervisor access the *32_EL2 sysregs KVM: arm64: Refine _EL2 system register list that require trap reinjection arm64: Add missing _EL2 encodings arm64: Add missing _EL12 encodings Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
2 parents 25a35c1 + 3f7915c commit 51e6079

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‎arch/arm64/include/asm/sysreg.h

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -270,6 +270,8 @@
270270
/* ETM */
271271
#define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
272272

273+
#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
274+
273275
#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
274276
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
275277
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
@@ -484,6 +486,7 @@
484486

485487
#define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
486488
#define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
489+
#define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
487490
#define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
488491
#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
489492
#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
@@ -497,10 +500,15 @@
497500
#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
498501

499502
#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
503+
#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
500504
#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
501505
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
502506
#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
503507
#define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
508+
#define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
509+
#define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
510+
#define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
511+
#define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3)
504512
#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
505513
#define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
506514
#define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
@@ -514,6 +522,18 @@
514522

515523
#define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
516524
#define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
525+
#define SYS_MPAMHCR_EL2 sys_reg(3, 4, 10, 4, 0)
526+
#define SYS_MPAMVPMV_EL2 sys_reg(3, 4, 10, 4, 1)
527+
#define SYS_MPAM2_EL2 sys_reg(3, 4, 10, 5, 0)
528+
#define __SYS__MPAMVPMx_EL2(x) sys_reg(3, 4, 10, 6, x)
529+
#define SYS_MPAMVPM0_EL2 __SYS__MPAMVPMx_EL2(0)
530+
#define SYS_MPAMVPM1_EL2 __SYS__MPAMVPMx_EL2(1)
531+
#define SYS_MPAMVPM2_EL2 __SYS__MPAMVPMx_EL2(2)
532+
#define SYS_MPAMVPM3_EL2 __SYS__MPAMVPMx_EL2(3)
533+
#define SYS_MPAMVPM4_EL2 __SYS__MPAMVPMx_EL2(4)
534+
#define SYS_MPAMVPM5_EL2 __SYS__MPAMVPMx_EL2(5)
535+
#define SYS_MPAMVPM6_EL2 __SYS__MPAMVPMx_EL2(6)
536+
#define SYS_MPAMVPM7_EL2 __SYS__MPAMVPMx_EL2(7)
517537

518538
#define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
519539
#define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
@@ -562,24 +582,49 @@
562582

563583
#define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
564584
#define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
585+
#define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
586+
587+
#define __AMEV_op2(m) (m & 0x7)
588+
#define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3))
589+
#define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
590+
#define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m)
591+
#define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
592+
#define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m)
565593

566594
#define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
567595
#define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
596+
#define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
597+
#define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
598+
#define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
599+
#define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
600+
#define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
601+
#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
568602

569603
/* VHE encodings for architectural EL0/1 system registers */
604+
#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
570605
#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
606+
#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
607+
#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
608+
#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
609+
#define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1)
610+
#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
571611
#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
572612
#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
573613
#define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
614+
#define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3)
574615
#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
575616
#define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
576617
#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
577618
#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
578619
#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
579620
#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
621+
#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
622+
#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
580623
#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
581624
#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
582625
#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
626+
#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
627+
#define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
583628
#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
584629
#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
585630
#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)

‎arch/arm64/kvm/emulate-nested.c

Lines changed: 71 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -648,15 +648,80 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
648648
SR_TRAP(SYS_APGAKEYLO_EL1, CGT_HCR_APK),
649649
SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK),
650650
/* All _EL2 registers */
651-
SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0),
652-
sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV),
651+
SR_TRAP(SYS_BRBCR_EL2, CGT_HCR_NV),
652+
SR_TRAP(SYS_VPIDR_EL2, CGT_HCR_NV),
653+
SR_TRAP(SYS_VMPIDR_EL2, CGT_HCR_NV),
654+
SR_TRAP(SYS_SCTLR_EL2, CGT_HCR_NV),
655+
SR_TRAP(SYS_ACTLR_EL2, CGT_HCR_NV),
656+
SR_TRAP(SYS_SCTLR2_EL2, CGT_HCR_NV),
657+
SR_RANGE_TRAP(SYS_HCR_EL2,
658+
SYS_HCRX_EL2, CGT_HCR_NV),
659+
SR_TRAP(SYS_SMPRIMAP_EL2, CGT_HCR_NV),
660+
SR_TRAP(SYS_SMCR_EL2, CGT_HCR_NV),
661+
SR_RANGE_TRAP(SYS_TTBR0_EL2,
662+
SYS_TCR2_EL2, CGT_HCR_NV),
663+
SR_TRAP(SYS_VTTBR_EL2, CGT_HCR_NV),
664+
SR_TRAP(SYS_VTCR_EL2, CGT_HCR_NV),
665+
SR_TRAP(SYS_VNCR_EL2, CGT_HCR_NV),
666+
SR_RANGE_TRAP(SYS_HDFGRTR_EL2,
667+
SYS_HAFGRTR_EL2, CGT_HCR_NV),
653668
/* Skip the SP_EL1 encoding... */
654669
SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV),
655670
SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV),
656-
SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1),
657-
sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV),
658-
SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0),
659-
sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV),
671+
/* Skip SPSR_irq, SPSR_abt, SPSR_und, SPSR_fiq */
672+
SR_TRAP(SYS_AFSR0_EL2, CGT_HCR_NV),
673+
SR_TRAP(SYS_AFSR1_EL2, CGT_HCR_NV),
674+
SR_TRAP(SYS_ESR_EL2, CGT_HCR_NV),
675+
SR_TRAP(SYS_VSESR_EL2, CGT_HCR_NV),
676+
SR_TRAP(SYS_TFSR_EL2, CGT_HCR_NV),
677+
SR_TRAP(SYS_FAR_EL2, CGT_HCR_NV),
678+
SR_TRAP(SYS_HPFAR_EL2, CGT_HCR_NV),
679+
SR_TRAP(SYS_PMSCR_EL2, CGT_HCR_NV),
680+
SR_TRAP(SYS_MAIR_EL2, CGT_HCR_NV),
681+
SR_TRAP(SYS_AMAIR_EL2, CGT_HCR_NV),
682+
SR_TRAP(SYS_MPAMHCR_EL2, CGT_HCR_NV),
683+
SR_TRAP(SYS_MPAMVPMV_EL2, CGT_HCR_NV),
684+
SR_TRAP(SYS_MPAM2_EL2, CGT_HCR_NV),
685+
SR_RANGE_TRAP(SYS_MPAMVPM0_EL2,
686+
SYS_MPAMVPM7_EL2, CGT_HCR_NV),
687+
/*
688+
* Note that the spec. describes a group of MEC registers
689+
* whose access should not trap, therefore skip the following:
690+
* MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2,
691+
* MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2,
692+
* VMECID_P_EL2.
693+
*/
694+
SR_RANGE_TRAP(SYS_VBAR_EL2,
695+
SYS_RMR_EL2, CGT_HCR_NV),
696+
SR_TRAP(SYS_VDISR_EL2, CGT_HCR_NV),
697+
/* ICH_AP0R<m>_EL2 */
698+
SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2,
699+
SYS_ICH_AP0R3_EL2, CGT_HCR_NV),
700+
/* ICH_AP1R<m>_EL2 */
701+
SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2,
702+
SYS_ICH_AP1R3_EL2, CGT_HCR_NV),
703+
SR_TRAP(SYS_ICC_SRE_EL2, CGT_HCR_NV),
704+
SR_RANGE_TRAP(SYS_ICH_HCR_EL2,
705+
SYS_ICH_EISR_EL2, CGT_HCR_NV),
706+
SR_TRAP(SYS_ICH_ELRSR_EL2, CGT_HCR_NV),
707+
SR_TRAP(SYS_ICH_VMCR_EL2, CGT_HCR_NV),
708+
/* ICH_LR<m>_EL2 */
709+
SR_RANGE_TRAP(SYS_ICH_LR0_EL2,
710+
SYS_ICH_LR15_EL2, CGT_HCR_NV),
711+
SR_TRAP(SYS_CONTEXTIDR_EL2, CGT_HCR_NV),
712+
SR_TRAP(SYS_TPIDR_EL2, CGT_HCR_NV),
713+
SR_TRAP(SYS_SCXTNUM_EL2, CGT_HCR_NV),
714+
/* AMEVCNTVOFF0<n>_EL2, AMEVCNTVOFF1<n>_EL2 */
715+
SR_RANGE_TRAP(SYS_AMEVCNTVOFF0n_EL2(0),
716+
SYS_AMEVCNTVOFF1n_EL2(15), CGT_HCR_NV),
717+
/* CNT*_EL2 */
718+
SR_TRAP(SYS_CNTVOFF_EL2, CGT_HCR_NV),
719+
SR_TRAP(SYS_CNTPOFF_EL2, CGT_HCR_NV),
720+
SR_TRAP(SYS_CNTHCTL_EL2, CGT_HCR_NV),
721+
SR_RANGE_TRAP(SYS_CNTHP_TVAL_EL2,
722+
SYS_CNTHP_CVAL_EL2, CGT_HCR_NV),
723+
SR_RANGE_TRAP(SYS_CNTHV_TVAL_EL2,
724+
SYS_CNTHV_CVAL_EL2, CGT_HCR_NV),
660725
/* All _EL02, _EL12 registers */
661726
SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
662727
sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),

‎arch/arm64/kvm/sys_regs.c

Lines changed: 17 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1795,8 +1795,8 @@ static unsigned int el2_visibility(const struct kvm_vcpu *vcpu,
17951795
* HCR_EL2.E2H==1, and only in the sysreg table for convenience of
17961796
* handling traps. Given that, they are always hidden from userspace.
17971797
*/
1798-
static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu,
1799-
const struct sys_reg_desc *rd)
1798+
static unsigned int hidden_user_visibility(const struct kvm_vcpu *vcpu,
1799+
const struct sys_reg_desc *rd)
18001800
{
18011801
return REG_HIDDEN_USER;
18021802
}
@@ -1807,7 +1807,7 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu,
18071807
.reset = rst, \
18081808
.reg = name##_EL1, \
18091809
.val = v, \
1810-
.visibility = elx2_visibility, \
1810+
.visibility = hidden_user_visibility, \
18111811
}
18121812

18131813
/*
@@ -1965,7 +1965,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
19651965
// DBGDTR[TR]X_EL0 share the same encoding
19661966
{ SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
19671967

1968-
{ SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1968+
{ SYS_DESC(SYS_DBGVCR32_EL2), trap_undef, reset_val, DBGVCR32_EL2, 0 },
19691969

19701970
{ SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
19711971

@@ -2384,18 +2384,28 @@ static const struct sys_reg_desc sys_reg_descs[] = {
23842384
EL2_REG(VTTBR_EL2, access_rw, reset_val, 0),
23852385
EL2_REG(VTCR_EL2, access_rw, reset_val, 0),
23862386

2387-
{ SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
2387+
{ SYS_DESC(SYS_DACR32_EL2), trap_undef, reset_unknown, DACR32_EL2 },
23882388
EL2_REG(HDFGRTR_EL2, access_rw, reset_val, 0),
23892389
EL2_REG(HDFGWTR_EL2, access_rw, reset_val, 0),
23902390
EL2_REG(SPSR_EL2, access_rw, reset_val, 0),
23912391
EL2_REG(ELR_EL2, access_rw, reset_val, 0),
23922392
{ SYS_DESC(SYS_SP_EL1), access_sp_el1},
23932393

2394-
{ SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
2394+
/* AArch32 SPSR_* are RES0 if trapped from a NV guest */
2395+
{ SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi,
2396+
.visibility = hidden_user_visibility },
2397+
{ SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi,
2398+
.visibility = hidden_user_visibility },
2399+
{ SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi,
2400+
.visibility = hidden_user_visibility },
2401+
{ SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi,
2402+
.visibility = hidden_user_visibility },
2403+
2404+
{ SYS_DESC(SYS_IFSR32_EL2), trap_undef, reset_unknown, IFSR32_EL2 },
23952405
EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
23962406
EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
23972407
EL2_REG(ESR_EL2, access_rw, reset_val, 0),
2398-
{ SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
2408+
{ SYS_DESC(SYS_FPEXC32_EL2), trap_undef, reset_val, FPEXC32_EL2, 0x700 },
23992409

24002410
EL2_REG(FAR_EL2, access_rw, reset_val, 0),
24012411
EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),

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