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Merge tag 'icc-6.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-linus
Georgi writes: interconnect fixes for v6.5-rc This contains a fix for a potential issue on some Qualcomm SoCs where bit-masks should have been used to configure the Bus Clock Manager hardware, instead of bandwidth units. - interconnect: qcom: Add support for mask-based BCMs - interconnect: qcom: sm8450: add enable_mask for bcm nodes - interconnect: qcom: sm8550: add enable_mask for bcm nodes - interconnect: qcom: sa8775p: add enable_mask for bcm nodes Signed-off-by: Georgi Djakov <djakov@kernel.org> * tag 'icc-6.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc: interconnect: qcom: sa8775p: add enable_mask for bcm nodes interconnect: qcom: sm8550: add enable_mask for bcm nodes interconnect: qcom: sm8450: add enable_mask for bcm nodes interconnect: qcom: Add support for mask-based BCMs
2 parents 77107b0 + 3cb11fe commit 51a26bb

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‎drivers/interconnect/qcom/bcm-voter.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,11 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm)
8383

8484
temp = agg_peak[bucket] * bcm->vote_scale;
8585
bcm->vote_y[bucket] = bcm_div(temp, bcm->aux_data.unit);
86+
87+
if (bcm->enable_mask && (bcm->vote_x[bucket] || bcm->vote_y[bucket])) {
88+
bcm->vote_x[bucket] = 0;
89+
bcm->vote_y[bucket] = bcm->enable_mask;
90+
}
8691
}
8792

8893
if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&

‎drivers/interconnect/qcom/icc-rpmh.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,7 @@ struct qcom_icc_node {
8181
* @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm
8282
* @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm
8383
* @vote_scale: scaling factor for vote_x and vote_y
84+
* @enable_mask: optional mask to send as vote instead of vote_x/vote_y
8485
* @dirty: flag used to indicate whether the bcm needs to be committed
8586
* @keepalive: flag used to indicate whether a keepalive is required
8687
* @aux_data: auxiliary data used when calculating threshold values and
@@ -97,6 +98,7 @@ struct qcom_icc_bcm {
9798
u64 vote_x[QCOM_ICC_NUM_BUCKETS];
9899
u64 vote_y[QCOM_ICC_NUM_BUCKETS];
99100
u64 vote_scale;
101+
u32 enable_mask;
100102
bool dirty;
101103
bool keepalive;
102104
struct bcm_db aux_data;

‎drivers/interconnect/qcom/sa8775p.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1873,6 +1873,7 @@ static struct qcom_icc_node srvc_snoc = {
18731873

18741874
static struct qcom_icc_bcm bcm_acv = {
18751875
.name = "ACV",
1876+
.enable_mask = 0x8,
18761877
.num_nodes = 1,
18771878
.nodes = { &ebi },
18781879
};

‎drivers/interconnect/qcom/sm8450.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1337,6 +1337,7 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = {
13371337

13381338
static struct qcom_icc_bcm bcm_acv = {
13391339
.name = "ACV",
1340+
.enable_mask = 0x8,
13401341
.num_nodes = 1,
13411342
.nodes = { &ebi },
13421343
};
@@ -1349,6 +1350,7 @@ static struct qcom_icc_bcm bcm_ce0 = {
13491350

13501351
static struct qcom_icc_bcm bcm_cn0 = {
13511352
.name = "CN0",
1353+
.enable_mask = 0x1,
13521354
.keepalive = true,
13531355
.num_nodes = 55,
13541356
.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
@@ -1383,6 +1385,7 @@ static struct qcom_icc_bcm bcm_cn0 = {
13831385

13841386
static struct qcom_icc_bcm bcm_co0 = {
13851387
.name = "CO0",
1388+
.enable_mask = 0x1,
13861389
.num_nodes = 2,
13871390
.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
13881391
};
@@ -1403,6 +1406,7 @@ static struct qcom_icc_bcm bcm_mm0 = {
14031406

14041407
static struct qcom_icc_bcm bcm_mm1 = {
14051408
.name = "MM1",
1409+
.enable_mask = 0x1,
14061410
.num_nodes = 12,
14071411
.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
14081412
&qnm_camnoc_sf, &qnm_mdp,
@@ -1445,6 +1449,7 @@ static struct qcom_icc_bcm bcm_sh0 = {
14451449

14461450
static struct qcom_icc_bcm bcm_sh1 = {
14471451
.name = "SH1",
1452+
.enable_mask = 0x1,
14481453
.num_nodes = 7,
14491454
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
14501455
&qnm_nsp_gemnoc, &qnm_pcie,
@@ -1461,6 +1466,7 @@ static struct qcom_icc_bcm bcm_sn0 = {
14611466

14621467
static struct qcom_icc_bcm bcm_sn1 = {
14631468
.name = "SN1",
1469+
.enable_mask = 0x1,
14641470
.num_nodes = 4,
14651471
.nodes = { &qhm_gic, &qxm_pimem,
14661472
&xm_gic, &qns_gemnoc_gc },
@@ -1492,6 +1498,7 @@ static struct qcom_icc_bcm bcm_sn7 = {
14921498

14931499
static struct qcom_icc_bcm bcm_acv_disp = {
14941500
.name = "ACV",
1501+
.enable_mask = 0x1,
14951502
.num_nodes = 1,
14961503
.nodes = { &ebi_disp },
14971504
};
@@ -1510,6 +1517,7 @@ static struct qcom_icc_bcm bcm_mm0_disp = {
15101517

15111518
static struct qcom_icc_bcm bcm_mm1_disp = {
15121519
.name = "MM1",
1520+
.enable_mask = 0x1,
15131521
.num_nodes = 3,
15141522
.nodes = { &qnm_mdp_disp, &qnm_rot_disp,
15151523
&qns_mem_noc_sf_disp },
@@ -1523,6 +1531,7 @@ static struct qcom_icc_bcm bcm_sh0_disp = {
15231531

15241532
static struct qcom_icc_bcm bcm_sh1_disp = {
15251533
.name = "SH1",
1534+
.enable_mask = 0x1,
15261535
.num_nodes = 1,
15271536
.nodes = { &qnm_pcie_disp },
15281537
};

‎drivers/interconnect/qcom/sm8550.c

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1473,6 +1473,7 @@ static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = {
14731473

14741474
static struct qcom_icc_bcm bcm_acv = {
14751475
.name = "ACV",
1476+
.enable_mask = 0x8,
14761477
.num_nodes = 1,
14771478
.nodes = { &ebi },
14781479
};
@@ -1485,6 +1486,7 @@ static struct qcom_icc_bcm bcm_ce0 = {
14851486

14861487
static struct qcom_icc_bcm bcm_cn0 = {
14871488
.name = "CN0",
1489+
.enable_mask = 0x1,
14881490
.keepalive = true,
14891491
.num_nodes = 54,
14901492
.nodes = { &qsm_cfg, &qhs_ahb2phy0,
@@ -1524,6 +1526,7 @@ static struct qcom_icc_bcm bcm_cn1 = {
15241526

15251527
static struct qcom_icc_bcm bcm_co0 = {
15261528
.name = "CO0",
1529+
.enable_mask = 0x1,
15271530
.num_nodes = 2,
15281531
.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
15291532
};
@@ -1549,6 +1552,7 @@ static struct qcom_icc_bcm bcm_mm0 = {
15491552

15501553
static struct qcom_icc_bcm bcm_mm1 = {
15511554
.name = "MM1",
1555+
.enable_mask = 0x1,
15521556
.num_nodes = 8,
15531557
.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
15541558
&qnm_camnoc_sf, &qnm_vapss_hcp,
@@ -1589,6 +1593,7 @@ static struct qcom_icc_bcm bcm_sh0 = {
15891593

15901594
static struct qcom_icc_bcm bcm_sh1 = {
15911595
.name = "SH1",
1596+
.enable_mask = 0x1,
15921597
.num_nodes = 13,
15931598
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
15941599
&chm_apps, &qnm_gpu,
@@ -1608,6 +1613,7 @@ static struct qcom_icc_bcm bcm_sn0 = {
16081613

16091614
static struct qcom_icc_bcm bcm_sn1 = {
16101615
.name = "SN1",
1616+
.enable_mask = 0x1,
16111617
.num_nodes = 3,
16121618
.nodes = { &qhm_gic, &xm_gic,
16131619
&qns_gemnoc_gc },
@@ -1633,6 +1639,7 @@ static struct qcom_icc_bcm bcm_sn7 = {
16331639

16341640
static struct qcom_icc_bcm bcm_acv_disp = {
16351641
.name = "ACV",
1642+
.enable_mask = 0x1,
16361643
.num_nodes = 1,
16371644
.nodes = { &ebi_disp },
16381645
};
@@ -1657,12 +1664,14 @@ static struct qcom_icc_bcm bcm_sh0_disp = {
16571664

16581665
static struct qcom_icc_bcm bcm_sh1_disp = {
16591666
.name = "SH1",
1667+
.enable_mask = 0x1,
16601668
.num_nodes = 2,
16611669
.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
16621670
};
16631671

16641672
static struct qcom_icc_bcm bcm_acv_cam_ife_0 = {
16651673
.name = "ACV",
1674+
.enable_mask = 0x0,
16661675
.num_nodes = 1,
16671676
.nodes = { &ebi_cam_ife_0 },
16681677
};
@@ -1681,6 +1690,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = {
16811690

16821691
static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = {
16831692
.name = "MM1",
1693+
.enable_mask = 0x1,
16841694
.num_nodes = 4,
16851695
.nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0,
16861696
&qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 },
@@ -1694,13 +1704,15 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = {
16941704

16951705
static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
16961706
.name = "SH1",
1707+
.enable_mask = 0x1,
16971708
.num_nodes = 3,
16981709
.nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0,
16991710
&qnm_pcie_cam_ife_0 },
17001711
};
17011712

17021713
static struct qcom_icc_bcm bcm_acv_cam_ife_1 = {
17031714
.name = "ACV",
1715+
.enable_mask = 0x0,
17041716
.num_nodes = 1,
17051717
.nodes = { &ebi_cam_ife_1 },
17061718
};
@@ -1719,6 +1731,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = {
17191731

17201732
static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = {
17211733
.name = "MM1",
1734+
.enable_mask = 0x1,
17221735
.num_nodes = 4,
17231736
.nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1,
17241737
&qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 },
@@ -1732,13 +1745,15 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = {
17321745

17331746
static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
17341747
.name = "SH1",
1748+
.enable_mask = 0x1,
17351749
.num_nodes = 3,
17361750
.nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1,
17371751
&qnm_pcie_cam_ife_1 },
17381752
};
17391753

17401754
static struct qcom_icc_bcm bcm_acv_cam_ife_2 = {
17411755
.name = "ACV",
1756+
.enable_mask = 0x0,
17421757
.num_nodes = 1,
17431758
.nodes = { &ebi_cam_ife_2 },
17441759
};
@@ -1757,6 +1772,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = {
17571772

17581773
static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = {
17591774
.name = "MM1",
1775+
.enable_mask = 0x1,
17601776
.num_nodes = 4,
17611777
.nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2,
17621778
&qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 },
@@ -1770,6 +1786,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = {
17701786

17711787
static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = {
17721788
.name = "SH1",
1789+
.enable_mask = 0x1,
17731790
.num_nodes = 3,
17741791
.nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2,
17751792
&qnm_pcie_cam_ife_2 },

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