Skip to content

Commit 50cf94b

Browse files
bebarinobebarino
committed
Merge tag 'clk-microchip-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip
Pull Microchip clk driver updates from Claudiu Beznea: Microchip AT91: - add generic clocks for U(S)ART available on SAMA5D2 SoCs Microchip Polarfire: - reset controller support for Polarfire clocks - .round_rate and .set rate support for clk-mpfs - code cleanup for clk-mpfs - PLL support for PolarFire SoC's Clock Conditioning Circuitry * tag 'clk-microchip-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: at91: sama5d2: Add Generic Clocks for UART/USART clk: microchip: add PolarFire SoC fabric clock support dt-bindings: clk: add PolarFire SoC fabric clock ids dt-bindings: clk: document PolarFire SoC fabric clocks dt-bindings: clk: rename mpfs-clkcfg binding clk: microchip: mpfs: update module authorship & licencing clk: microchip: mpfs: convert periph_clk to clk_gate clk: microchip: mpfs: convert cfg_clk to clk_divider clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() clk: microchip: mpfs: simplify control reg access clk: microchip: mpfs: move id & offset out of clock structs clk: microchip: mpfs: add MSS pll's set & round rate MAINTAINERS: add polarfire soc reset controller reset: add polarfire soc reset support clk: microchip: mpfs: add reset controller dt-bindings: clk: microchip: mpfs: add reset controller support clk: microchip: mpfs: make the rtc's ahb clock critical clk: microchip: mpfs: fix clk_cfg array bounds violation
2 parents 568035b + 935edf0 commit 50cf94b

File tree

13 files changed

+788
-195
lines changed

13 files changed

+788
-195
lines changed

‎Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,80 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
8+
9+
maintainers:
10+
- Conor Dooley <conor.dooley@microchip.com>
11+
12+
description: |
13+
Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
14+
these blocks contains two PLLs and 2 DLLs & are located in the four corners of
15+
the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
16+
https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
17+
18+
properties:
19+
compatible:
20+
const: microchip,mpfs-ccc
21+
22+
reg:
23+
items:
24+
- description: PLL0's control registers
25+
- description: PLL1's control registers
26+
- description: DLL0's control registers
27+
- description: DLL1's control registers
28+
29+
clocks:
30+
description:
31+
The CCC PLL's have two input clocks. It is required that even if the input
32+
clocks are identical that both are provided.
33+
minItems: 2
34+
items:
35+
- description: PLL0's refclk0
36+
- description: PLL0's refclk1
37+
- description: PLL1's refclk0
38+
- description: PLL1's refclk1
39+
- description: DLL0's refclk
40+
- description: DLL1's refclk
41+
42+
clock-names:
43+
minItems: 2
44+
items:
45+
- const: pll0_ref0
46+
- const: pll0_ref1
47+
- const: pll1_ref0
48+
- const: pll1_ref1
49+
- const: dll0_ref
50+
- const: dll1_ref
51+
52+
'#clock-cells':
53+
const: 1
54+
description: |
55+
The clock consumer should specify the desired clock by having the clock
56+
ID in its "clocks" phandle cell.
57+
See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
58+
PolarFire clock IDs.
59+
60+
required:
61+
- compatible
62+
- reg
63+
- clocks
64+
- clock-names
65+
- '#clock-cells'
66+
67+
additionalProperties: false
68+
69+
examples:
70+
- |
71+
clock-controller@38100000 {
72+
compatible = "microchip,mpfs-ccc";
73+
reg = <0x38010000 0x1000>, <0x38020000 0x1000>,
74+
<0x39010000 0x1000>, <0x39020000 0x1000>;
75+
#clock-cells = <1>;
76+
clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
77+
<&refclk_ccc>, <&refclk_ccc>;
78+
clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
79+
"dll0_ref", "dll1_ref";
80+
};

‎Documentation/devicetree/bindings/clock/microchip,mpfs.yaml renamed to ‎Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml

Lines changed: 16 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
22
%YAML 1.2
33
---
4-
$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#
4+
$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
55
$schema: http://devicetree.org/meta-schemas/core.yaml#
66

77
title: Microchip PolarFire Clock Control Module Binding
@@ -40,8 +40,21 @@ properties:
4040
const: 1
4141
description: |
4242
The clock consumer should specify the desired clock by having the clock
43-
ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
44-
for the full list of PolarFire clock IDs.
43+
ID in its "clocks" phandle cell.
44+
See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
45+
PolarFire clock IDs.
46+
47+
resets:
48+
maxItems: 1
49+
50+
'#reset-cells':
51+
description:
52+
The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
53+
CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
54+
peripheral via the clock ID in its "resets" phandle cell.
55+
See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
56+
PolarFire clock IDs.
57+
const: 1
4558

4659
required:
4760
- compatible

‎MAINTAINERS

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17532,6 +17532,7 @@ F: drivers/char/hw_random/mpfs-rng.c
1753217532
F: drivers/clk/microchip/clk-mpfs.c
1753317533
F: drivers/mailbox/mailbox-mpfs.c
1753417534
F: drivers/pci/controller/pcie-microchip-host.c
17535+
F: drivers/reset/reset-mpfs.c
1753517536
F: drivers/rtc/rtc-mpfs.c
1753617537
F: drivers/soc/microchip/
1753717538
F: drivers/spi/spi-microchip-core.c

‎drivers/clk/at91/sama5d2.c

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -120,6 +120,16 @@ static const struct {
120120
struct clk_range r;
121121
int chg_pid;
122122
} sama5d2_gck[] = {
123+
{ .n = "flx0_gclk", .id = 19, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
124+
{ .n = "flx1_gclk", .id = 20, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
125+
{ .n = "flx2_gclk", .id = 21, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
126+
{ .n = "flx3_gclk", .id = 22, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
127+
{ .n = "flx4_gclk", .id = 23, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
128+
{ .n = "uart0_gclk", .id = 24, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
129+
{ .n = "uart1_gclk", .id = 25, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
130+
{ .n = "uart2_gclk", .id = 26, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
131+
{ .n = "uart3_gclk", .id = 27, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
132+
{ .n = "uart4_gclk", .id = 28, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
123133
{ .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },
124134
{ .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },
125135
{ .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },

‎drivers/clk/microchip/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,5 +6,6 @@ config COMMON_CLK_PIC32
66
config MCHP_CLK_MPFS
77
bool "Clk driver for PolarFire SoC"
88
depends on (RISCV && SOC_MICROCHIP_POLARFIRE) || COMPILE_TEST
9+
select AUXILIARY_BUS
910
help
1011
Supports Clock Configuration for PolarFire SoC

‎drivers/clk/microchip/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,3 +2,4 @@
22
obj-$(CONFIG_COMMON_CLK_PIC32) += clk-core.o
33
obj-$(CONFIG_PIC32MZDA) += clk-pic32mzda.o
44
obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs.o
5+
obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs-ccc.o

0 commit comments

Comments
 (0)