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#define IMX7D_M4_STOP (IMX7D_ENABLE_M4 | IMX7D_SW_M4C_RST | \
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IMX7D_SW_M4C_NON_SCLR_RST)
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+ #define IMX8M_M7_STOP (IMX7D_ENABLE_M4 | IMX7D_SW_M4C_RST)
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+ #define IMX8M_M7_POLL IMX7D_ENABLE_M4
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+
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+ #define IMX8M_GPR22 0x58
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+ #define IMX8M_GPR22_CM7_CPUWAIT BIT(0)
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+
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/* Address: 0x020D8000 */
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#define IMX6SX_SRC_SCR 0x00
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#define IMX6SX_ENABLE_M4 BIT(22)
@@ -91,6 +97,7 @@ static int imx_rproc_detach_pd(struct rproc *rproc);
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struct imx_rproc {
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struct device * dev ;
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struct regmap * regmap ;
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+ struct regmap * gpr ;
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struct rproc * rproc ;
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const struct imx_rproc_dcfg * dcfg ;
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struct imx_rproc_mem mem [IMX_RPROC_MEM_MAX ];
@@ -285,6 +292,18 @@ static const struct imx_rproc_att imx_rproc_att_imx6sx[] = {
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{ 0x80000000 , 0x80000000 , 0x60000000 , 0 },
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};
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+ static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mn_mmio = {
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+ .src_reg = IMX7D_SRC_SCR ,
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+ .src_mask = IMX7D_M4_RST_MASK ,
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+ .src_start = IMX7D_M4_START ,
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+ .src_stop = IMX8M_M7_STOP ,
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+ .gpr_reg = IMX8M_GPR22 ,
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+ .gpr_wait = IMX8M_GPR22_CM7_CPUWAIT ,
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+ .att = imx_rproc_att_imx8mn ,
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+ .att_size = ARRAY_SIZE (imx_rproc_att_imx8mn ),
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+ .method = IMX_RPROC_MMIO ,
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+ };
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+
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static const struct imx_rproc_dcfg imx_rproc_cfg_imx8mn = {
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.att = imx_rproc_att_imx8mn ,
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.att_size = ARRAY_SIZE (imx_rproc_att_imx8mn ),
@@ -365,8 +384,14 @@ static int imx_rproc_start(struct rproc *rproc)
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switch (dcfg -> method ) {
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case IMX_RPROC_MMIO :
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- ret = regmap_update_bits (priv -> regmap , dcfg -> src_reg , dcfg -> src_mask ,
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- dcfg -> src_start );
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+ if (priv -> gpr ) {
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+ ret = regmap_clear_bits (priv -> gpr , dcfg -> gpr_reg ,
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+ dcfg -> gpr_wait );
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+ } else {
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+ ret = regmap_update_bits (priv -> regmap , dcfg -> src_reg ,
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+ dcfg -> src_mask ,
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+ dcfg -> src_start );
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+ }
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break ;
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case IMX_RPROC_SMC :
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arm_smccc_smc (IMX_SIP_RPROC , IMX_SIP_RPROC_START , 0 , 0 , 0 , 0 , 0 , 0 , & res );
@@ -395,6 +420,16 @@ static int imx_rproc_stop(struct rproc *rproc)
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switch (dcfg -> method ) {
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case IMX_RPROC_MMIO :
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+ if (priv -> gpr ) {
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+ ret = regmap_set_bits (priv -> gpr , dcfg -> gpr_reg ,
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+ dcfg -> gpr_wait );
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+ if (ret ) {
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+ dev_err (priv -> dev ,
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+ "Failed to quiescence M4 platform!\n" );
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+ return ret ;
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+ }
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+ }
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+
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ret = regmap_update_bits (priv -> regmap , dcfg -> src_reg , dcfg -> src_mask ,
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dcfg -> src_stop );
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break ;
@@ -992,6 +1027,10 @@ static int imx_rproc_detect_mode(struct imx_rproc *priv)
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break ;
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}
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+ priv -> gpr = syscon_regmap_lookup_by_phandle (dev -> of_node , "fsl,iomuxc-gpr" );
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+ if (IS_ERR (priv -> gpr ))
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+ priv -> gpr = NULL ;
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+
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regmap = syscon_regmap_lookup_by_phandle (dev -> of_node , "syscon" );
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if (IS_ERR (regmap )) {
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dev_err (dev , "failed to find syscon\n" );
@@ -1001,6 +1040,19 @@ static int imx_rproc_detect_mode(struct imx_rproc *priv)
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priv -> regmap = regmap ;
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regmap_attach_dev (dev , regmap , & config );
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+ if (priv -> gpr ) {
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+ ret = regmap_read (priv -> gpr , dcfg -> gpr_reg , & val );
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+ if (val & dcfg -> gpr_wait ) {
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+ /*
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+ * After cold boot, the CM indicates its in wait
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+ * state, but not fully powered off. Power it off
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+ * fully so firmware can be loaded into it.
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+ */
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+ imx_rproc_stop (priv -> rproc );
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+ return 0 ;
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+ }
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+ }
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+
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ret = regmap_read (regmap , dcfg -> src_reg , & val );
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if (ret ) {
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dev_err (dev , "Failed to read src\n" );
@@ -1142,6 +1194,8 @@ static const struct of_device_id imx_rproc_of_match[] = {
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{ .compatible = "fsl,imx8mm-cm4" , .data = & imx_rproc_cfg_imx8mq },
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{ .compatible = "fsl,imx8mn-cm7" , .data = & imx_rproc_cfg_imx8mn },
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{ .compatible = "fsl,imx8mp-cm7" , .data = & imx_rproc_cfg_imx8mn },
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+ { .compatible = "fsl,imx8mn-cm7-mmio" , .data = & imx_rproc_cfg_imx8mn_mmio },
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+ { .compatible = "fsl,imx8mp-cm7-mmio" , .data = & imx_rproc_cfg_imx8mn_mmio },
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{ .compatible = "fsl,imx8qxp-cm4" , .data = & imx_rproc_cfg_imx8qxp },
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{ .compatible = "fsl,imx8qm-cm4" , .data = & imx_rproc_cfg_imx8qm },
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{ .compatible = "fsl,imx8ulp-cm33" , .data = & imx_rproc_cfg_imx8ulp },
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