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clk: zynqmp: replace warn_once with pr_debug for failed clock ops
The warning that a clock operation failed is only printed once. However, the function is called for various different clocks. The limit hides the warnings if different clocks are affected by the failures. The clock ops might fail if the firmware that handles the clocks is misconfigured. Therefore, replace the pr_warn_once with pr_debug to allow the user to see all errors if necessary. By default, hide the error messages and let drivers handle the errors. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20220119115434.2042017-1-m.tretter@pengutronix.de Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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4 files changed

+32
-32
lines changed

4 files changed

+32
-32
lines changed

‎drivers/clk/zynqmp/clk-gate-zynqmp.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,8 @@ static int zynqmp_clk_gate_enable(struct clk_hw *hw)
4141
ret = zynqmp_pm_clock_enable(clk_id);
4242

4343
if (ret)
44-
pr_warn_once("%s() clock enabled failed for %s, ret = %d\n",
45-
__func__, clk_name, ret);
44+
pr_debug("%s() clock enable failed for %s (id %d), ret = %d\n",
45+
__func__, clk_name, clk_id, ret);
4646

4747
return ret;
4848
}
@@ -61,8 +61,8 @@ static void zynqmp_clk_gate_disable(struct clk_hw *hw)
6161
ret = zynqmp_pm_clock_disable(clk_id);
6262

6363
if (ret)
64-
pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
65-
__func__, clk_name, ret);
64+
pr_debug("%s() clock disable failed for %s (id %d), ret = %d\n",
65+
__func__, clk_name, clk_id, ret);
6666
}
6767

6868
/**
@@ -80,8 +80,8 @@ static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw)
8080

8181
ret = zynqmp_pm_clock_getstate(clk_id, &state);
8282
if (ret) {
83-
pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
84-
__func__, clk_name, ret);
83+
pr_debug("%s() clock get state failed for %s, ret = %d\n",
84+
__func__, clk_name, ret);
8585
return -EIO;
8686
}
8787

‎drivers/clk/zynqmp/clk-mux-zynqmp.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -51,8 +51,8 @@ static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw)
5151
ret = zynqmp_pm_clock_getparent(clk_id, &val);
5252

5353
if (ret) {
54-
pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n",
55-
__func__, clk_name, ret);
54+
pr_debug("%s() getparent failed for clock: %s, ret = %d\n",
55+
__func__, clk_name, ret);
5656
/*
5757
* clk_core_get_parent_by_index() takes num_parents as incorrect
5858
* index which is exactly what I want to return here
@@ -80,8 +80,8 @@ static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index)
8080
ret = zynqmp_pm_clock_setparent(clk_id, index);
8181

8282
if (ret)
83-
pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n",
84-
__func__, clk_name, ret);
83+
pr_debug("%s() set parent failed for clock: %s, ret = %d\n",
84+
__func__, clk_name, ret);
8585

8686
return ret;
8787
}

‎drivers/clk/zynqmp/divider.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -89,8 +89,8 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
8989
ret = zynqmp_pm_clock_getdivider(clk_id, &div);
9090

9191
if (ret)
92-
pr_warn_once("%s() get divider failed for %s, ret = %d\n",
93-
__func__, clk_name, ret);
92+
pr_debug("%s() get divider failed for %s, ret = %d\n",
93+
__func__, clk_name, ret);
9494

9595
if (div_type == TYPE_DIV1)
9696
value = div & 0xFFFF;
@@ -177,8 +177,8 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
177177
ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv);
178178

179179
if (ret)
180-
pr_warn_once("%s() get divider failed for %s, ret = %d\n",
181-
__func__, clk_name, ret);
180+
pr_debug("%s() get divider failed for %s, ret = %d\n",
181+
__func__, clk_name, ret);
182182
if (div_type == TYPE_DIV1)
183183
bestdiv = bestdiv & 0xFFFF;
184184
else
@@ -244,8 +244,8 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
244244
ret = zynqmp_pm_clock_setdivider(clk_id, div);
245245

246246
if (ret)
247-
pr_warn_once("%s() set divider failed for %s, ret = %d\n",
248-
__func__, clk_name, ret);
247+
pr_debug("%s() set divider failed for %s, ret = %d\n",
248+
__func__, clk_name, ret);
249249

250250
return ret;
251251
}

‎drivers/clk/zynqmp/pll.c

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -56,8 +56,8 @@ static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw)
5656

5757
ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload);
5858
if (ret) {
59-
pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n",
60-
__func__, clk_name, ret);
59+
pr_debug("%s() PLL get frac mode failed for %s, ret = %d\n",
60+
__func__, clk_name, ret);
6161
return PLL_MODE_ERROR;
6262
}
6363

@@ -84,8 +84,8 @@ static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on)
8484

8585
ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode);
8686
if (ret)
87-
pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n",
88-
__func__, clk_name, ret);
87+
pr_debug("%s() PLL set frac mode failed for %s, ret = %d\n",
88+
__func__, clk_name, ret);
8989
else
9090
clk->set_pll_mode = true;
9191
}
@@ -145,8 +145,8 @@ static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw,
145145

146146
ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv);
147147
if (ret) {
148-
pr_warn_once("%s() get divider failed for %s, ret = %d\n",
149-
__func__, clk_name, ret);
148+
pr_debug("%s() get divider failed for %s, ret = %d\n",
149+
__func__, clk_name, ret);
150150
return 0ul;
151151
}
152152

@@ -200,8 +200,8 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
200200
WARN(1, "More than allowed devices are using the %s, which is forbidden\n",
201201
clk_name);
202202
else if (ret)
203-
pr_warn_once("%s() set divider failed for %s, ret = %d\n",
204-
__func__, clk_name, ret);
203+
pr_debug("%s() set divider failed for %s, ret = %d\n",
204+
__func__, clk_name, ret);
205205
zynqmp_pm_set_pll_frac_data(clk_id, f);
206206

207207
return rate + frac;
@@ -211,8 +211,8 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
211211
fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
212212
ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv);
213213
if (ret)
214-
pr_warn_once("%s() set divider failed for %s, ret = %d\n",
215-
__func__, clk_name, ret);
214+
pr_debug("%s() set divider failed for %s, ret = %d\n",
215+
__func__, clk_name, ret);
216216

217217
return parent_rate * fbdiv;
218218
}
@@ -233,8 +233,8 @@ static int zynqmp_pll_is_enabled(struct clk_hw *hw)
233233

234234
ret = zynqmp_pm_clock_getstate(clk_id, &state);
235235
if (ret) {
236-
pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
237-
__func__, clk_name, ret);
236+
pr_debug("%s() clock get state failed for %s, ret = %d\n",
237+
__func__, clk_name, ret);
238238
return -EIO;
239239
}
240240

@@ -265,8 +265,8 @@ static int zynqmp_pll_enable(struct clk_hw *hw)
265265

266266
ret = zynqmp_pm_clock_enable(clk_id);
267267
if (ret)
268-
pr_warn_once("%s() clock enable failed for %s, ret = %d\n",
269-
__func__, clk_name, ret);
268+
pr_debug("%s() clock enable failed for %s, ret = %d\n",
269+
__func__, clk_name, ret);
270270

271271
return ret;
272272
}
@@ -287,8 +287,8 @@ static void zynqmp_pll_disable(struct clk_hw *hw)
287287

288288
ret = zynqmp_pm_clock_disable(clk_id);
289289
if (ret)
290-
pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
291-
__func__, clk_name, ret);
290+
pr_debug("%s() clock disable failed for %s, ret = %d\n",
291+
__func__, clk_name, ret);
292292
}
293293

294294
static const struct clk_ops zynqmp_pll_ops = {

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