|
676 | 676 | status = "disabled";
|
677 | 677 | };
|
678 | 678 |
|
679 |
| - qspi: spi@13010000 { |
680 |
| - compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; |
681 |
| - reg = <0x0 0x13010000 0x0 0x10000>, |
682 |
| - <0x0 0x21000000 0x0 0x400000>; |
683 |
| - interrupts = <25>; |
684 |
| - clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, |
685 |
| - <&syscrg JH7110_SYSCLK_QSPI_AHB>, |
686 |
| - <&syscrg JH7110_SYSCLK_QSPI_APB>; |
687 |
| - clock-names = "ref", "ahb", "apb"; |
688 |
| - resets = <&syscrg JH7110_SYSRST_QSPI_APB>, |
689 |
| - <&syscrg JH7110_SYSRST_QSPI_AHB>, |
690 |
| - <&syscrg JH7110_SYSRST_QSPI_REF>; |
691 |
| - reset-names = "qspi", "qspi-ocp", "rstc_ref"; |
692 |
| - cdns,fifo-depth = <256>; |
693 |
| - cdns,fifo-width = <4>; |
694 |
| - cdns,trigger-address = <0x0>; |
695 |
| - status = "disabled"; |
696 |
| - }; |
697 |
| - |
698 | 679 | spi3: spi@12070000 {
|
699 | 680 | compatible = "arm,pl022", "arm,primecell";
|
700 | 681 | reg = <0x0 0x12070000 0x0 0x10000>;
|
|
767 | 748 | #thermal-sensor-cells = <0>;
|
768 | 749 | };
|
769 | 750 |
|
| 751 | + qspi: spi@13010000 { |
| 752 | + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; |
| 753 | + reg = <0x0 0x13010000 0x0 0x10000>, |
| 754 | + <0x0 0x21000000 0x0 0x400000>; |
| 755 | + interrupts = <25>; |
| 756 | + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, |
| 757 | + <&syscrg JH7110_SYSCLK_QSPI_AHB>, |
| 758 | + <&syscrg JH7110_SYSCLK_QSPI_APB>; |
| 759 | + clock-names = "ref", "ahb", "apb"; |
| 760 | + resets = <&syscrg JH7110_SYSRST_QSPI_APB>, |
| 761 | + <&syscrg JH7110_SYSRST_QSPI_AHB>, |
| 762 | + <&syscrg JH7110_SYSRST_QSPI_REF>; |
| 763 | + reset-names = "qspi", "qspi-ocp", "rstc_ref"; |
| 764 | + cdns,fifo-depth = <256>; |
| 765 | + cdns,fifo-width = <4>; |
| 766 | + cdns,trigger-address = <0x0>; |
| 767 | + status = "disabled"; |
| 768 | + }; |
| 769 | + |
770 | 770 | syscrg: clock-controller@13020000 {
|
771 | 771 | compatible = "starfive,jh7110-syscrg";
|
772 | 772 | reg = <0x0 0x13020000 0x0 0x10000>;
|
|
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