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Merge tag 'mediatek-drm-fixes-20241028' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-fixes
Mediatek DRM Fixes - 20241028 1. Fix degradation problem of alpha blending 2. Fix color format MACROs in OVL 3. Fix get efuse issue for MT8188 DPTX 4. Fix potential NULL dereference in mtk_crtc_destroy() 5. Correct dpi power-domains property 6. Add split subschema property constraints Signed-off-by: Dave Airlie <airlied@redhat.com> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20241028135846.3570-1-chunkuang.hu@kernel.org
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Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml

Lines changed: 10 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,16 @@ properties:
6363
- const: sleep
6464

6565
power-domains:
66+
description: |
67+
The MediaTek DPI module is typically associated with one of the
68+
following multimedia power domains:
69+
POWER_DOMAIN_DISPLAY
70+
POWER_DOMAIN_VDOSYS
71+
POWER_DOMAIN_MM
72+
The specific power domain used varies depending on the SoC design.
73+
74+
It is recommended to explicitly add the appropriate power domain
75+
property to the DPI node in the device tree.
6676
maxItems: 1
6777

6878
port:
@@ -79,20 +89,6 @@ required:
7989
- clock-names
8090
- port
8191

82-
allOf:
83-
- if:
84-
not:
85-
properties:
86-
compatible:
87-
contains:
88-
enum:
89-
- mediatek,mt6795-dpi
90-
- mediatek,mt8173-dpi
91-
- mediatek,mt8186-dpi
92-
then:
93-
properties:
94-
power-domains: false
95-
9692
additionalProperties: false
9793

9894
examples:

Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@ properties:
3838
description: A phandle and PM domain specifier as defined by bindings of
3939
the power controller specified by phandle. See
4040
Documentation/devicetree/bindings/power/power-domain.yaml for details.
41+
maxItems: 1
4142

4243
mediatek,gce-client-reg:
4344
description:
@@ -57,6 +58,9 @@ properties:
5758
clocks:
5859
items:
5960
- description: SPLIT Clock
61+
- description: Used for interfacing with the HDMI RX signal source.
62+
- description: Paired with receiving HDMI RX metadata.
63+
minItems: 1
6064

6165
required:
6266
- compatible
@@ -72,9 +76,24 @@ allOf:
7276
const: mediatek,mt8195-mdp3-split
7377

7478
then:
79+
properties:
80+
clocks:
81+
minItems: 3
82+
7583
required:
7684
- mediatek,gce-client-reg
7785

86+
- if:
87+
properties:
88+
compatible:
89+
contains:
90+
const: mediatek,mt8173-disp-split
91+
92+
then:
93+
properties:
94+
clocks:
95+
maxItems: 1
96+
7897
additionalProperties: false
7998

8099
examples:

drivers/gpu/drm/mediatek/mtk_crtc.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -127,9 +127,8 @@ static void mtk_crtc_destroy(struct drm_crtc *crtc)
127127

128128
mtk_mutex_put(mtk_crtc->mutex);
129129
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
130-
cmdq_pkt_destroy(&mtk_crtc->cmdq_client, &mtk_crtc->cmdq_handle);
131-
132130
if (mtk_crtc->cmdq_client.chan) {
131+
cmdq_pkt_destroy(&mtk_crtc->cmdq_client, &mtk_crtc->cmdq_handle);
133132
mbox_free_channel(mtk_crtc->cmdq_client.chan);
134133
mtk_crtc->cmdq_client.chan = NULL;
135134
}
@@ -913,6 +912,7 @@ static int mtk_crtc_init_comp_planes(struct drm_device *drm_dev,
913912
BIT(pipe),
914913
mtk_crtc_plane_type(mtk_crtc->layer_nr, num_planes),
915914
mtk_ddp_comp_supported_rotations(comp),
915+
mtk_ddp_comp_get_blend_modes(comp),
916916
mtk_ddp_comp_get_formats(comp),
917917
mtk_ddp_comp_get_num_formats(comp), i);
918918
if (ret)

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -363,6 +363,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
363363
.layer_config = mtk_ovl_layer_config,
364364
.bgclr_in_on = mtk_ovl_bgclr_in_on,
365365
.bgclr_in_off = mtk_ovl_bgclr_in_off,
366+
.get_blend_modes = mtk_ovl_get_blend_modes,
366367
.get_formats = mtk_ovl_get_formats,
367368
.get_num_formats = mtk_ovl_get_num_formats,
368369
};
@@ -416,6 +417,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
416417
.disconnect = mtk_ovl_adaptor_disconnect,
417418
.add = mtk_ovl_adaptor_add_comp,
418419
.remove = mtk_ovl_adaptor_remove_comp,
420+
.get_blend_modes = mtk_ovl_adaptor_get_blend_modes,
419421
.get_formats = mtk_ovl_adaptor_get_formats,
420422
.get_num_formats = mtk_ovl_adaptor_get_num_formats,
421423
.mode_valid = mtk_ovl_adaptor_mode_valid,

drivers/gpu/drm/mediatek/mtk_ddp_comp.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,7 @@ struct mtk_ddp_comp_funcs {
8080
void (*ctm_set)(struct device *dev,
8181
struct drm_crtc_state *state);
8282
struct device * (*dma_dev_get)(struct device *dev);
83+
u32 (*get_blend_modes)(struct device *dev);
8384
const u32 *(*get_formats)(struct device *dev);
8485
size_t (*get_num_formats)(struct device *dev);
8586
void (*connect)(struct device *dev, struct device *mmsys_dev, unsigned int next);
@@ -266,6 +267,15 @@ static inline struct device *mtk_ddp_comp_dma_dev_get(struct mtk_ddp_comp *comp)
266267
return comp->dev;
267268
}
268269

270+
static inline
271+
u32 mtk_ddp_comp_get_blend_modes(struct mtk_ddp_comp *comp)
272+
{
273+
if (comp->funcs && comp->funcs->get_blend_modes)
274+
return comp->funcs->get_blend_modes(comp->dev);
275+
276+
return 0;
277+
}
278+
269279
static inline
270280
const u32 *mtk_ddp_comp_get_formats(struct mtk_ddp_comp *comp)
271281
{

drivers/gpu/drm/mediatek/mtk_disp_drv.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,7 @@ void mtk_ovl_register_vblank_cb(struct device *dev,
103103
void mtk_ovl_unregister_vblank_cb(struct device *dev);
104104
void mtk_ovl_enable_vblank(struct device *dev);
105105
void mtk_ovl_disable_vblank(struct device *dev);
106+
u32 mtk_ovl_get_blend_modes(struct device *dev);
106107
const u32 *mtk_ovl_get_formats(struct device *dev);
107108
size_t mtk_ovl_get_num_formats(struct device *dev);
108109

@@ -131,6 +132,7 @@ void mtk_ovl_adaptor_start(struct device *dev);
131132
void mtk_ovl_adaptor_stop(struct device *dev);
132133
unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
133134
struct device *mtk_ovl_adaptor_dma_dev_get(struct device *dev);
135+
u32 mtk_ovl_adaptor_get_blend_modes(struct device *dev);
134136
const u32 *mtk_ovl_adaptor_get_formats(struct device *dev);
135137
size_t mtk_ovl_adaptor_get_num_formats(struct device *dev);
136138
enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

Lines changed: 55 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -65,8 +65,8 @@
6565
#define OVL_CON_CLRFMT_RGB (1 << 12)
6666
#define OVL_CON_CLRFMT_ARGB8888 (2 << 12)
6767
#define OVL_CON_CLRFMT_RGBA8888 (3 << 12)
68-
#define OVL_CON_CLRFMT_ABGR8888 (OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP)
69-
#define OVL_CON_CLRFMT_BGRA8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP)
68+
#define OVL_CON_CLRFMT_ABGR8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP)
69+
#define OVL_CON_CLRFMT_BGRA8888 (OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP)
7070
#define OVL_CON_CLRFMT_UYVY (4 << 12)
7171
#define OVL_CON_CLRFMT_YUYV (5 << 12)
7272
#define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
@@ -146,6 +146,7 @@ struct mtk_disp_ovl_data {
146146
bool fmt_rgb565_is_0;
147147
bool smi_id_en;
148148
bool supports_afbc;
149+
const u32 blend_modes;
149150
const u32 *formats;
150151
size_t num_formats;
151152
bool supports_clrfmt_ext;
@@ -214,6 +215,13 @@ void mtk_ovl_disable_vblank(struct device *dev)
214215
writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);
215216
}
216217

218+
u32 mtk_ovl_get_blend_modes(struct device *dev)
219+
{
220+
struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
221+
222+
return ovl->data->blend_modes;
223+
}
224+
217225
const u32 *mtk_ovl_get_formats(struct device *dev)
218226
{
219227
struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
@@ -386,14 +394,27 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int idx,
386394
DISP_REG_OVL_RDMA_CTRL(idx));
387395
}
388396

389-
static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt,
390-
unsigned int blend_mode)
397+
static unsigned int mtk_ovl_fmt_convert(struct mtk_disp_ovl *ovl,
398+
struct mtk_plane_state *state)
391399
{
392-
/* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
393-
* is defined in mediatek HW data sheet.
394-
* The alphabet order in XXX is no relation to data
395-
* arrangement in memory.
400+
unsigned int fmt = state->pending.format;
401+
unsigned int blend_mode = DRM_MODE_BLEND_COVERAGE;
402+
403+
/*
404+
* For the platforms where OVL_CON_CLRFMT_MAN is defined in the hardware data sheet
405+
* and supports premultiplied color formats, such as OVL_CON_CLRFMT_PARGB8888.
406+
*
407+
* Check blend_modes in the driver data to see if premultiplied mode is supported.
408+
* If not, use coverage mode instead to set it to the supported color formats.
409+
*
410+
* Current DRM assumption is that alpha is default premultiplied, so the bitmask of
411+
* blend_modes must include BIT(DRM_MODE_BLEND_PREMULTI). Otherwise, mtk_plane_init()
412+
* will get an error return from drm_plane_create_blend_mode_property() and
413+
* state->base.pixel_blend_mode should not be used.
396414
*/
415+
if (ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI))
416+
blend_mode = state->base.pixel_blend_mode;
417+
397418
switch (fmt) {
398419
default:
399420
case DRM_FORMAT_RGB565:
@@ -471,20 +492,26 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
471492
return;
472493
}
473494

474-
con = ovl_fmt_convert(ovl, fmt, blend_mode);
495+
con = mtk_ovl_fmt_convert(ovl, state);
475496
if (state->base.fb) {
476-
con |= OVL_CON_AEN;
477497
con |= state->base.alpha & OVL_CON_ALPHA;
478-
}
479498

480-
/* CONST_BLD must be enabled for XRGB formats although the alpha channel
481-
* can be ignored, or OVL will still read the value from memory.
482-
* For RGB888 related formats, whether CONST_BLD is enabled or not won't
483-
* affect the result. Therefore we use !has_alpha as the condition.
484-
*/
485-
if ((state->base.fb && !state->base.fb->format->has_alpha) ||
486-
blend_mode == DRM_MODE_BLEND_PIXEL_NONE)
487-
ignore_pixel_alpha = OVL_CONST_BLEND;
499+
/*
500+
* For blend_modes supported SoCs, always enable alpha blending.
501+
* For blend_modes unsupported SoCs, enable alpha blending when has_alpha is set.
502+
*/
503+
if (blend_mode || state->base.fb->format->has_alpha)
504+
con |= OVL_CON_AEN;
505+
506+
/*
507+
* Although the alpha channel can be ignored, CONST_BLD must be enabled
508+
* for XRGB format, otherwise OVL will still read the value from memory.
509+
* For RGB888 related formats, whether CONST_BLD is enabled or not won't
510+
* affect the result. Therefore we use !has_alpha as the condition.
511+
*/
512+
if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE || !state->base.fb->format->has_alpha)
513+
ignore_pixel_alpha = OVL_CONST_BLEND;
514+
}
488515

489516
if (pending->rotation & DRM_MODE_REFLECT_Y) {
490517
con |= OVL_CON_VIRT_FLIP;
@@ -663,6 +690,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
663690
.layer_nr = 4,
664691
.fmt_rgb565_is_0 = true,
665692
.smi_id_en = true,
693+
.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
694+
BIT(DRM_MODE_BLEND_COVERAGE) |
695+
BIT(DRM_MODE_BLEND_PIXEL_NONE),
666696
.formats = mt8173_formats,
667697
.num_formats = ARRAY_SIZE(mt8173_formats),
668698
};
@@ -673,6 +703,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
673703
.layer_nr = 2,
674704
.fmt_rgb565_is_0 = true,
675705
.smi_id_en = true,
706+
.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
707+
BIT(DRM_MODE_BLEND_COVERAGE) |
708+
BIT(DRM_MODE_BLEND_PIXEL_NONE),
676709
.formats = mt8173_formats,
677710
.num_formats = ARRAY_SIZE(mt8173_formats),
678711
};
@@ -684,6 +717,9 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
684717
.fmt_rgb565_is_0 = true,
685718
.smi_id_en = true,
686719
.supports_afbc = true,
720+
.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
721+
BIT(DRM_MODE_BLEND_COVERAGE) |
722+
BIT(DRM_MODE_BLEND_PIXEL_NONE),
687723
.formats = mt8195_formats,
688724
.num_formats = ARRAY_SIZE(mt8195_formats),
689725
.supports_clrfmt_ext = true,

drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -400,6 +400,13 @@ void mtk_ovl_adaptor_disable_vblank(struct device *dev)
400400
mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
401401
}
402402

403+
u32 mtk_ovl_adaptor_get_blend_modes(struct device *dev)
404+
{
405+
struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
406+
407+
return mtk_ethdr_get_blend_modes(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
408+
}
409+
403410
const u32 *mtk_ovl_adaptor_get_formats(struct device *dev)
404411
{
405412
struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);

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