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arm64/arm: arm_pmuv3: perf: Don't truncate 64-bit registers
The driver used to truncate several 64-bit registers such as PMCEID[n] registers used to describe whether architectural and microarchitectural events in range 0x4000-0x401f exist. Due to discarding the bits, the driver made the events invisible, even if they existed. Moreover, PMCCFILTR and PMCR registers have additional bits in the upper 32 bits. This patch makes them available although they aren't currently used. Finally, functions handling PMXEVCNTR and PMXEVTYPER registers are removed as they not being used at all. Fixes: df29ddf ("arm64: perf: Abstract system register accesses away") Reported-by: Carl Worth <carl@os.amperecomputing.com> Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Acked-by: Will Deacon <will@kernel.org> Closes: https://lore.kernel.org/.. Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20231102183012.1251410-1-ilkka@os.amperecomputing.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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-48
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3 files changed

+31
-48
lines changed

arch/arm/include/asm/arm_pmuv3.h

Lines changed: 23 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,8 @@
2323
#define PMUSERENR __ACCESS_CP15(c9, 0, c14, 0)
2424
#define PMINTENSET __ACCESS_CP15(c9, 0, c14, 1)
2525
#define PMINTENCLR __ACCESS_CP15(c9, 0, c14, 2)
26+
#define PMCEID2 __ACCESS_CP15(c9, 0, c14, 4)
27+
#define PMCEID3 __ACCESS_CP15(c9, 0, c14, 5)
2628
#define PMMIR __ACCESS_CP15(c9, 0, c14, 6)
2729
#define PMCCFILTR __ACCESS_CP15(c14, 0, c15, 7)
2830

@@ -150,21 +152,6 @@ static inline u64 read_pmccntr(void)
150152
return read_sysreg(PMCCNTR);
151153
}
152154

153-
static inline void write_pmxevcntr(u32 val)
154-
{
155-
write_sysreg(val, PMXEVCNTR);
156-
}
157-
158-
static inline u32 read_pmxevcntr(void)
159-
{
160-
return read_sysreg(PMXEVCNTR);
161-
}
162-
163-
static inline void write_pmxevtyper(u32 val)
164-
{
165-
write_sysreg(val, PMXEVTYPER);
166-
}
167-
168155
static inline void write_pmcntenset(u32 val)
169156
{
170157
write_sysreg(val, PMCNTENSET);
@@ -205,16 +192,6 @@ static inline void write_pmuserenr(u32 val)
205192
write_sysreg(val, PMUSERENR);
206193
}
207194

208-
static inline u32 read_pmceid0(void)
209-
{
210-
return read_sysreg(PMCEID0);
211-
}
212-
213-
static inline u32 read_pmceid1(void)
214-
{
215-
return read_sysreg(PMCEID1);
216-
}
217-
218195
static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
219196
static inline void kvm_clr_pmu_events(u32 clr) {}
220197
static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
@@ -231,6 +208,7 @@ static inline void kvm_vcpu_pmu_resync_el0(void) {}
231208

232209
/* PMU Version in DFR Register */
233210
#define ARMV8_PMU_DFR_VER_NI 0
211+
#define ARMV8_PMU_DFR_VER_V3P1 0x4
234212
#define ARMV8_PMU_DFR_VER_V3P4 0x5
235213
#define ARMV8_PMU_DFR_VER_V3P5 0x6
236214
#define ARMV8_PMU_DFR_VER_IMP_DEF 0xF
@@ -251,4 +229,24 @@ static inline bool is_pmuv3p5(int pmuver)
251229
return pmuver >= ARMV8_PMU_DFR_VER_V3P5;
252230
}
253231

232+
static inline u64 read_pmceid0(void)
233+
{
234+
u64 val = read_sysreg(PMCEID0);
235+
236+
if (read_pmuver() >= ARMV8_PMU_DFR_VER_V3P1)
237+
val |= (u64)read_sysreg(PMCEID2) << 32;
238+
239+
return val;
240+
}
241+
242+
static inline u64 read_pmceid1(void)
243+
{
244+
u64 val = read_sysreg(PMCEID1);
245+
246+
if (read_pmuver() >= ARMV8_PMU_DFR_VER_V3P1)
247+
val |= (u64)read_sysreg(PMCEID3) << 32;
248+
249+
return val;
250+
}
251+
254252
#endif

arch/arm64/include/asm/arm_pmuv3.h

Lines changed: 5 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -46,12 +46,12 @@ static inline u32 read_pmuver(void)
4646
ID_AA64DFR0_EL1_PMUVer_SHIFT);
4747
}
4848

49-
static inline void write_pmcr(u32 val)
49+
static inline void write_pmcr(u64 val)
5050
{
5151
write_sysreg(val, pmcr_el0);
5252
}
5353

54-
static inline u32 read_pmcr(void)
54+
static inline u64 read_pmcr(void)
5555
{
5656
return read_sysreg(pmcr_el0);
5757
}
@@ -71,21 +71,6 @@ static inline u64 read_pmccntr(void)
7171
return read_sysreg(pmccntr_el0);
7272
}
7373

74-
static inline void write_pmxevcntr(u32 val)
75-
{
76-
write_sysreg(val, pmxevcntr_el0);
77-
}
78-
79-
static inline u32 read_pmxevcntr(void)
80-
{
81-
return read_sysreg(pmxevcntr_el0);
82-
}
83-
84-
static inline void write_pmxevtyper(u32 val)
85-
{
86-
write_sysreg(val, pmxevtyper_el0);
87-
}
88-
8974
static inline void write_pmcntenset(u32 val)
9075
{
9176
write_sysreg(val, pmcntenset_el0);
@@ -106,7 +91,7 @@ static inline void write_pmintenclr(u32 val)
10691
write_sysreg(val, pmintenclr_el1);
10792
}
10893

109-
static inline void write_pmccfiltr(u32 val)
94+
static inline void write_pmccfiltr(u64 val)
11095
{
11196
write_sysreg(val, pmccfiltr_el0);
11297
}
@@ -126,12 +111,12 @@ static inline void write_pmuserenr(u32 val)
126111
write_sysreg(val, pmuserenr_el0);
127112
}
128113

129-
static inline u32 read_pmceid0(void)
114+
static inline u64 read_pmceid0(void)
130115
{
131116
return read_sysreg(pmceid0_el0);
132117
}
133118

134-
static inline u32 read_pmceid1(void)
119+
static inline u64 read_pmceid1(void)
135120
{
136121
return read_sysreg(pmceid1_el0);
137122
}

drivers/perf/arm_pmuv3.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -428,12 +428,12 @@ static inline bool armv8pmu_event_is_chained(struct perf_event *event)
428428
#define ARMV8_IDX_TO_COUNTER(x) \
429429
(((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
430430

431-
static inline u32 armv8pmu_pmcr_read(void)
431+
static inline u64 armv8pmu_pmcr_read(void)
432432
{
433433
return read_pmcr();
434434
}
435435

436-
static inline void armv8pmu_pmcr_write(u32 val)
436+
static inline void armv8pmu_pmcr_write(u64 val)
437437
{
438438
val &= ARMV8_PMU_PMCR_MASK;
439439
isb();
@@ -957,7 +957,7 @@ static int armv8pmu_set_event_filter(struct hw_perf_event *event,
957957
static void armv8pmu_reset(void *info)
958958
{
959959
struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
960-
u32 pmcr;
960+
u64 pmcr;
961961

962962
/* The counter and interrupt enable registers are unknown at reset. */
963963
armv8pmu_disable_counter(U32_MAX);

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