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Merge tag 'drm-msm-next-2023-08-20' of https://gitlab.freedesktop.org/drm/msm into drm-next
Updates for v6.6, which includes a backmerge of msm-fixes to avoid conficts. Core: - SM6125 MDSS support DPU: - SM6125 DPU support - Added subblocks to display snapshot - Use UBWC data from MDSS driver rather than duplicating it - dpu_core_perf cleanup DSI: - Enabled burst mode to fix CMD mode panels - Runtime PM support - refgen regulator support DSI PHY: - SM6125 support in 14nm DSI PHY driver GPU: - Rework GPU identification to prepare for a7xx, and other a7xx prep - Cleanups and fixes - Disallow legacy relocs on a6xx and newer - a690: switch to using a660_gmu.bin fw as this is what we have in linux-firmware and we see no evidence that it should be different from other a660 family (a6xx subgen 4) devices - Submit overhead opts, 1.6x faster for NO_IMPLICIT_SYNC commits with 100 BOs to 2.5x faster for 1000 BOs Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGv_01g-edjdfKLWWcb-rO5aSyLsv5FpbKrTkXVL9+ngTQ@mail.gmail.com
2 parents fdebffe + 34b149e commit 38f8873

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‎Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml

Lines changed: 22 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ properties:
2929
- description: Link clock from DP PHY
3030
- description: VCO DIV clock from DP PHY
3131
- description: AHB config clock from GCC
32+
- description: GPLL0 div source from GCC
3233

3334
clock-names:
3435
items:
@@ -39,13 +40,24 @@ properties:
3940
- const: dp_phy_pll_link_clk
4041
- const: dp_phy_pll_vco_div_clk
4142
- const: cfg_ahb_clk
43+
- const: gcc_disp_gpll0_div_clk_src
4244

4345
'#clock-cells':
4446
const: 1
4547

4648
'#power-domain-cells':
4749
const: 1
4850

51+
power-domains:
52+
description:
53+
A phandle and PM domain specifier for the CX power domain.
54+
maxItems: 1
55+
56+
required-opps:
57+
description:
58+
A phandle to an OPP node describing the power domain's performance point.
59+
maxItems: 1
60+
4961
reg:
5062
maxItems: 1
5163

@@ -63,23 +75,31 @@ examples:
6375
- |
6476
#include <dt-bindings/clock/qcom,rpmcc.h>
6577
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
78+
#include <dt-bindings/power/qcom-rpmpd.h>
6679
clock-controller@5f00000 {
6780
compatible = "qcom,sm6125-dispcc";
6881
reg = <0x5f00000 0x20000>;
82+
6983
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
7084
<&dsi0_phy 0>,
7185
<&dsi0_phy 1>,
7286
<&dsi1_phy 1>,
7387
<&dp_phy 0>,
7488
<&dp_phy 1>,
75-
<&gcc GCC_DISP_AHB_CLK>;
89+
<&gcc GCC_DISP_AHB_CLK>,
90+
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
7691
clock-names = "bi_tcxo",
7792
"dsi0_phy_pll_out_byteclk",
7893
"dsi0_phy_pll_out_dsiclk",
7994
"dsi1_phy_pll_out_dsiclk",
8095
"dp_phy_pll_link_clk",
8196
"dp_phy_pll_vco_div_clk",
82-
"cfg_ahb_clk";
97+
"cfg_ahb_clk",
98+
"gcc_disp_gpll0_div_clk_src";
99+
100+
required-opps = <&rpmhpd_opp_ret>;
101+
power-domains = <&rpmpd SM6125_VDDCX>;
102+
83103
#clock-cells = <1>;
84104
#power-domain-cells = <1>;
85105
};

‎Documentation/devicetree/bindings/display/msm/dp-controller.yaml

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Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ properties:
2828
- qcom,sm8350-dp
2929
- items:
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- enum:
31+
- qcom,sm8250-dp
3132
- qcom,sm8450-dp
3233
- qcom,sm8550-dp
3334
- const: qcom,sm8350-dp

‎Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ properties:
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- qcom,sdm660-dsi-ctrl
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- qcom,sdm845-dsi-ctrl
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- qcom,sm6115-dsi-ctrl
30+
- qcom,sm6125-dsi-ctrl
3031
- qcom,sm6350-dsi-ctrl
3132
- qcom,sm6375-dsi-ctrl
3233
- qcom,sm8150-dsi-ctrl
@@ -166,6 +167,10 @@ properties:
166167
description:
167168
Phandle to vdd regulator device node
168169

170+
refgen-supply:
171+
description:
172+
Phandle to REFGEN regulator device node
173+
169174
vcca-supply:
170175
description:
171176
Phandle to vdd regulator device node
@@ -301,6 +306,7 @@ allOf:
301306
contains:
302307
enum:
303308
- qcom,msm8998-dsi-ctrl
309+
- qcom,sm6125-dsi-ctrl
304310
- qcom,sm6350-dsi-ctrl
305311
then:
306312
properties:

‎Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@ properties:
1919
- qcom,dsi-phy-14nm-2290
2020
- qcom,dsi-phy-14nm-660
2121
- qcom,dsi-phy-14nm-8953
22+
- qcom,sm6125-dsi-phy-14nm
2223

2324
reg:
2425
items:
@@ -35,6 +36,16 @@ properties:
3536
vcca-supply:
3637
description: Phandle to vcca regulator device node.
3738

39+
power-domains:
40+
description:
41+
A phandle and PM domain specifier for an optional power domain.
42+
maxItems: 1
43+
44+
required-opps:
45+
description:
46+
A phandle to an OPP node describing the power domain's performance point.
47+
maxItems: 1
48+
3849
required:
3950
- compatible
4051
- reg

‎Documentation/devicetree/bindings/display/msm/gpu.yaml

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,12 @@ maintainers:
1313
properties:
1414
compatible:
1515
oneOf:
16+
- description: |
17+
The driver is parsing the compat string for Adreno to
18+
figure out the chip-id.
19+
items:
20+
- pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'
21+
- const: qcom,adreno
1622
- description: |
1723
The driver is parsing the compat string for Adreno to
1824
figure out the gpu-id and patch level.

‎Documentation/devicetree/bindings/display/msm/mdss-common.yaml

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Original file line numberDiff line numberDiff line change
@@ -77,6 +77,12 @@ properties:
7777
items:
7878
- description: MDSS_CORE reset
7979

80+
memory-region:
81+
maxItems: 1
82+
description:
83+
Phandle to a node describing a reserved framebuffer memory region.
84+
For example, the splash memory region set up by the bootloader.
85+
8086
required:
8187
- reg
8288
- reg-names

‎Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ properties:
1515
compatible:
1616
enum:
1717
- qcom,sc7180-dpu
18+
- qcom,sm6125-dpu
1819
- qcom,sm6350-dpu
1920
- qcom,sm6375-dpu
2021

@@ -63,7 +64,9 @@ allOf:
6364
- if:
6465
properties:
6566
compatible:
66-
const: qcom,sm6375-dpu
67+
enum:
68+
- qcom,sm6375-dpu
69+
- qcom,sm6125-dpu
6770

6871
then:
6972
properties:

‎Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml

Lines changed: 213 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,213 @@
1+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm SM6125 Display MDSS
8+
9+
maintainers:
10+
- Marijn Suijten <marijn.suijten@somainline.org>
11+
12+
description:
13+
SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14+
like DPU display controller, DSI and DP interfaces etc.
15+
16+
$ref: /schemas/display/msm/mdss-common.yaml#
17+
18+
properties:
19+
compatible:
20+
const: qcom,sm6125-mdss
21+
22+
clocks:
23+
items:
24+
- description: Display AHB clock from gcc
25+
- description: Display AHB clock
26+
- description: Display core clock
27+
28+
clock-names:
29+
items:
30+
- const: iface
31+
- const: ahb
32+
- const: core
33+
34+
iommus:
35+
maxItems: 1
36+
37+
interconnects:
38+
maxItems: 2
39+
40+
interconnect-names:
41+
maxItems: 2
42+
43+
patternProperties:
44+
"^display-controller@[0-9a-f]+$":
45+
type: object
46+
properties:
47+
compatible:
48+
const: qcom,sm6125-dpu
49+
50+
"^dsi@[0-9a-f]+$":
51+
type: object
52+
properties:
53+
compatible:
54+
items:
55+
- const: qcom,sm6125-dsi-ctrl
56+
- const: qcom,mdss-dsi-ctrl
57+
58+
"^phy@[0-9a-f]+$":
59+
type: object
60+
properties:
61+
compatible:
62+
const: qcom,sm6125-dsi-phy-14nm
63+
64+
unevaluatedProperties: false
65+
66+
examples:
67+
- |
68+
#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
69+
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
70+
#include <dt-bindings/clock/qcom,rpmcc.h>
71+
#include <dt-bindings/interrupt-controller/arm-gic.h>
72+
#include <dt-bindings/power/qcom-rpmpd.h>
73+
74+
display-subsystem@5e00000 {
75+
compatible = "qcom,sm6125-mdss";
76+
reg = <0x05e00000 0x1000>;
77+
reg-names = "mdss";
78+
79+
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
80+
interrupt-controller;
81+
#interrupt-cells = <1>;
82+
83+
clocks = <&gcc GCC_DISP_AHB_CLK>,
84+
<&dispcc DISP_CC_MDSS_AHB_CLK>,
85+
<&dispcc DISP_CC_MDSS_MDP_CLK>;
86+
clock-names = "iface",
87+
"ahb",
88+
"core";
89+
90+
power-domains = <&dispcc MDSS_GDSC>;
91+
92+
iommus = <&apps_smmu 0x400 0x0>;
93+
94+
#address-cells = <1>;
95+
#size-cells = <1>;
96+
ranges;
97+
98+
display-controller@5e01000 {
99+
compatible = "qcom,sm6125-dpu";
100+
reg = <0x05e01000 0x83208>,
101+
<0x05eb0000 0x2008>;
102+
reg-names = "mdp", "vbif";
103+
104+
interrupt-parent = <&mdss>;
105+
interrupts = <0>;
106+
107+
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
108+
<&dispcc DISP_CC_MDSS_AHB_CLK>,
109+
<&dispcc DISP_CC_MDSS_ROT_CLK>,
110+
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
111+
<&dispcc DISP_CC_MDSS_MDP_CLK>,
112+
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
113+
<&gcc GCC_DISP_THROTTLE_CORE_CLK>;
114+
clock-names = "bus",
115+
"iface",
116+
"rot",
117+
"lut",
118+
"core",
119+
"vsync",
120+
"throttle";
121+
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
122+
assigned-clock-rates = <19200000>;
123+
124+
operating-points-v2 = <&mdp_opp_table>;
125+
power-domains = <&rpmpd SM6125_VDDCX>;
126+
127+
ports {
128+
#address-cells = <1>;
129+
#size-cells = <0>;
130+
131+
port@0 {
132+
reg = <0>;
133+
dpu_intf1_out: endpoint {
134+
remote-endpoint = <&mdss_dsi0_in>;
135+
};
136+
};
137+
};
138+
};
139+
140+
dsi@5e94000 {
141+
compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
142+
reg = <0x05e94000 0x400>;
143+
reg-names = "dsi_ctrl";
144+
145+
interrupt-parent = <&mdss>;
146+
interrupts = <4>;
147+
148+
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
149+
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
150+
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
151+
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
152+
<&dispcc DISP_CC_MDSS_AHB_CLK>,
153+
<&gcc GCC_DISP_HF_AXI_CLK>;
154+
clock-names = "byte",
155+
"byte_intf",
156+
"pixel",
157+
"core",
158+
"iface",
159+
"bus";
160+
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
161+
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
162+
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
163+
164+
operating-points-v2 = <&dsi_opp_table>;
165+
power-domains = <&rpmpd SM6125_VDDCX>;
166+
167+
phys = <&mdss_dsi0_phy>;
168+
phy-names = "dsi";
169+
170+
#address-cells = <1>;
171+
#size-cells = <0>;
172+
173+
ports {
174+
#address-cells = <1>;
175+
#size-cells = <0>;
176+
177+
port@0 {
178+
reg = <0>;
179+
mdss_dsi0_in: endpoint {
180+
remote-endpoint = <&dpu_intf1_out>;
181+
};
182+
};
183+
184+
port@1 {
185+
reg = <1>;
186+
mdss_dsi0_out: endpoint {
187+
};
188+
};
189+
};
190+
};
191+
192+
phy@5e94400 {
193+
compatible = "qcom,sm6125-dsi-phy-14nm";
194+
reg = <0x05e94400 0x100>,
195+
<0x05e94500 0x300>,
196+
<0x05e94800 0x188>;
197+
reg-names = "dsi_phy",
198+
"dsi_phy_lane",
199+
"dsi_pll";
200+
201+
#clock-cells = <1>;
202+
#phy-cells = <0>;
203+
204+
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
205+
<&rpmcc RPM_SMD_XO_CLK_SRC>;
206+
clock-names = "iface",
207+
"ref";
208+
209+
required-opps = <&rpmpd_opp_nom>;
210+
power-domains = <&rpmpd SM6125_VDDMX>;
211+
};
212+
};
213+
...

‎Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml

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Original file line numberDiff line numberDiff line change
@@ -131,13 +131,6 @@ examples:
131131
remote-endpoint = <&dsi0_in>;
132132
};
133133
};
134-
135-
port@1 {
136-
reg = <1>;
137-
dpu_intf2_out: endpoint {
138-
remote-endpoint = <&dsi1_in>;
139-
};
140-
};
141134
};
142135
};
143136

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