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KVM: riscv: selftests: Add exception handling support
Add the infrastructure for guest exception handling in riscv selftests. Customized handlers can be enabled by vm_install_exception_handler(vector) or vm_install_interrupt_handler(). The code is inspired from that of x86/arm64. Signed-off-by: Haibo Xu <haibo1.xu@intel.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
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‎tools/testing/selftests/kvm/Makefile

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@@ -53,6 +53,7 @@ LIBKVM_s390x += lib/s390x/diag318_test_handler.c
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LIBKVM_s390x += lib/s390x/processor.c
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LIBKVM_s390x += lib/s390x/ucall.c
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LIBKVM_riscv += lib/riscv/handlers.S
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LIBKVM_riscv += lib/riscv/processor.c
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LIBKVM_riscv += lib/riscv/ucall.c
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‎tools/testing/selftests/kvm/include/riscv/processor.h

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@@ -48,6 +48,56 @@ static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t subtype,
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KVM_REG_RISCV_SBI_SINGLE, \
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idx, KVM_REG_SIZE_ULONG)
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struct ex_regs {
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unsigned long ra;
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unsigned long sp;
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unsigned long gp;
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unsigned long tp;
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unsigned long t0;
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unsigned long t1;
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unsigned long t2;
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unsigned long s0;
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unsigned long s1;
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unsigned long a0;
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unsigned long a1;
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unsigned long a2;
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unsigned long a3;
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unsigned long a4;
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unsigned long a5;
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unsigned long a6;
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unsigned long a7;
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unsigned long s2;
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unsigned long s3;
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unsigned long s4;
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unsigned long s5;
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unsigned long s6;
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unsigned long s7;
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unsigned long s8;
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unsigned long s9;
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unsigned long s10;
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unsigned long s11;
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unsigned long t3;
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unsigned long t4;
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unsigned long t5;
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unsigned long t6;
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unsigned long epc;
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unsigned long status;
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unsigned long cause;
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};
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#define NR_VECTORS 2
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#define NR_EXCEPTIONS 32
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#define EC_MASK (NR_EXCEPTIONS - 1)
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typedef void(*exception_handler_fn)(struct ex_regs *);
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void vm_init_vector_tables(struct kvm_vm *vm);
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void vcpu_init_vector_tables(struct kvm_vcpu *vcpu);
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void vm_install_exception_handler(struct kvm_vm *vm, int vector, exception_handler_fn handler);
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void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn handler);
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/* L3 index Bit[47:39] */
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#define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL
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#define PGTBL_L3_INDEX_SHIFT 39

‎tools/testing/selftests/kvm/lib/riscv/handlers.S

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,101 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023 Intel Corporation
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*/
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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#endif
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#include <asm/csr.h>
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.macro save_context
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addi sp, sp, (-8*34)
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sd x1, 0(sp)
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sd x2, 8(sp)
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sd x3, 16(sp)
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sd x4, 24(sp)
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sd x5, 32(sp)
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sd x6, 40(sp)
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sd x7, 48(sp)
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sd x8, 56(sp)
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sd x9, 64(sp)
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sd x10, 72(sp)
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sd x11, 80(sp)
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sd x12, 88(sp)
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sd x13, 96(sp)
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sd x14, 104(sp)
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sd x15, 112(sp)
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sd x16, 120(sp)
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sd x17, 128(sp)
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sd x18, 136(sp)
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sd x19, 144(sp)
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sd x20, 152(sp)
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sd x21, 160(sp)
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sd x22, 168(sp)
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sd x23, 176(sp)
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sd x24, 184(sp)
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sd x25, 192(sp)
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sd x26, 200(sp)
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sd x27, 208(sp)
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sd x28, 216(sp)
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sd x29, 224(sp)
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sd x30, 232(sp)
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sd x31, 240(sp)
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csrr s0, CSR_SEPC
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csrr s1, CSR_SSTATUS
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csrr s2, CSR_SCAUSE
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sd s0, 248(sp)
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sd s1, 256(sp)
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sd s2, 264(sp)
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.endm
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.macro restore_context
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ld s2, 264(sp)
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ld s1, 256(sp)
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ld s0, 248(sp)
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csrw CSR_SCAUSE, s2
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csrw CSR_SSTATUS, s1
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csrw CSR_SEPC, s0
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ld x31, 240(sp)
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ld x30, 232(sp)
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ld x29, 224(sp)
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ld x28, 216(sp)
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ld x27, 208(sp)
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ld x26, 200(sp)
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ld x25, 192(sp)
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ld x24, 184(sp)
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ld x23, 176(sp)
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ld x22, 168(sp)
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ld x21, 160(sp)
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ld x20, 152(sp)
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ld x19, 144(sp)
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ld x18, 136(sp)
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ld x17, 128(sp)
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ld x16, 120(sp)
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ld x15, 112(sp)
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ld x14, 104(sp)
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ld x13, 96(sp)
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ld x12, 88(sp)
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ld x11, 80(sp)
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ld x10, 72(sp)
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ld x9, 64(sp)
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ld x8, 56(sp)
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ld x7, 48(sp)
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ld x6, 40(sp)
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ld x5, 32(sp)
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ld x4, 24(sp)
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ld x3, 16(sp)
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ld x2, 8(sp)
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ld x1, 0(sp)
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addi sp, sp, (8*34)
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.endm
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.balign 4
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.global exception_vectors
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exception_vectors:
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save_context
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move a0, sp
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call route_exception
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restore_context
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sret

‎tools/testing/selftests/kvm/lib/riscv/processor.c

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Original file line numberDiff line numberDiff line change
@@ -13,6 +13,8 @@
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#define DEFAULT_RISCV_GUEST_STACK_VADDR_MIN 0xac0000
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static vm_vaddr_t exception_handlers;
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static uint64_t page_align(struct kvm_vm *vm, uint64_t v)
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{
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return (v + vm->page_size) & ~(vm->page_size - 1);
@@ -364,8 +366,75 @@ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...)
364366
va_end(ap);
365367
}
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void kvm_exit_unexpected_exception(int vector, int ec)
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{
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ucall(UCALL_UNHANDLED, 2, vector, ec);
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}
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void assert_on_unhandled_exception(struct kvm_vcpu *vcpu)
368375
{
376+
struct ucall uc;
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378+
if (get_ucall(vcpu, &uc) == UCALL_UNHANDLED) {
379+
TEST_FAIL("Unexpected exception (vector:0x%lx, ec:0x%lx)",
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uc.args[0], uc.args[1]);
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}
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}
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struct handlers {
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exception_handler_fn exception_handlers[NR_VECTORS][NR_EXCEPTIONS];
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};
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void route_exception(struct ex_regs *regs)
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{
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struct handlers *handlers = (struct handlers *)exception_handlers;
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int vector = 0, ec;
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ec = regs->cause & ~CAUSE_IRQ_FLAG;
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if (ec >= NR_EXCEPTIONS)
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goto unexpected_exception;
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/* Use the same handler for all the interrupts */
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if (regs->cause & CAUSE_IRQ_FLAG) {
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vector = 1;
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ec = 0;
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}
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if (handlers && handlers->exception_handlers[vector][ec])
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return handlers->exception_handlers[vector][ec](regs);
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unexpected_exception:
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return kvm_exit_unexpected_exception(vector, ec);
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}
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void vcpu_init_vector_tables(struct kvm_vcpu *vcpu)
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{
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extern char exception_vectors;
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vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(stvec), (unsigned long)&exception_vectors);
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}
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void vm_init_vector_tables(struct kvm_vm *vm)
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{
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vm->handlers = __vm_vaddr_alloc(vm, sizeof(struct handlers),
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vm->page_size, MEM_REGION_DATA);
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*(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers;
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}
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void vm_install_exception_handler(struct kvm_vm *vm, int vector, exception_handler_fn handler)
426+
{
427+
struct handlers *handlers = addr_gva2hva(vm, vm->handlers);
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assert(vector < NR_EXCEPTIONS);
430+
handlers->exception_handlers[0][vector] = handler;
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}
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void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn handler)
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{
435+
struct handlers *handlers = addr_gva2hva(vm, vm->handlers);
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437+
handlers->exception_handlers[1][0] = handler;
369438
}
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371440
struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,

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