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Harshit Shahalexandrebelloni
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i3c: master: cdns: Update maximum prescaler value for i2c clock
As per the Cadence IP document fixed the I2C clock divider value limit from 16 bits instead of 10 bits. Without this change setting up the I2C clock to low frequencies will not work as the prescaler value might be greater than 10 bit number. I3C clock divider value is 10 bits only. Updating the macro names for both. Signed-off-by: Harshit Shah <harshitshah.opendev@gmail.com> Link: https://lore.kernel.org/r/1703927483-28682-1-git-send-email-harshitshah.opendev@gmail.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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drivers/i3c/master/i3c-master-cdns.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,8 @@
7676
#define PRESCL_CTRL0 0x14
7777
#define PRESCL_CTRL0_I2C(x) ((x) << 16)
7878
#define PRESCL_CTRL0_I3C(x) (x)
79-
#define PRESCL_CTRL0_MAX GENMASK(9, 0)
79+
#define PRESCL_CTRL0_I3C_MAX GENMASK(9, 0)
80+
#define PRESCL_CTRL0_I2C_MAX GENMASK(15, 0)
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8182
#define PRESCL_CTRL1 0x18
8283
#define PRESCL_CTRL1_PP_LOW_MASK GENMASK(15, 8)
@@ -1233,7 +1234,7 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m)
12331234
return -EINVAL;
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pres = DIV_ROUND_UP(sysclk_rate, (bus->scl_rate.i3c * 4)) - 1;
1236-
if (pres > PRESCL_CTRL0_MAX)
1237+
if (pres > PRESCL_CTRL0_I3C_MAX)
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return -ERANGE;
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bus->scl_rate.i3c = sysclk_rate / ((pres + 1) * 4);
@@ -1246,7 +1247,7 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m)
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max_i2cfreq = bus->scl_rate.i2c;
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pres = (sysclk_rate / (max_i2cfreq * 5)) - 1;
1249-
if (pres > PRESCL_CTRL0_MAX)
1250+
if (pres > PRESCL_CTRL0_I2C_MAX)
12501251
return -ERANGE;
12511252

12521253
bus->scl_rate.i2c = sysclk_rate / ((pres + 1) * 5);

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