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#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
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#define PP_POLICY_MASK 0x1F
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+ /*
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+ * SPR has different layout for Psys Domain PowerLimit registers.
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+ * There are 17 bits of PL1 and PL2 instead of 15 bits.
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+ * The Enable bits and TimeWindow bits are also shifted as a result.
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+ */
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+ #define PSYS_POWER_LIMIT1_MASK 0x1FFFF
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+ #define PSYS_POWER_LIMIT1_ENABLE BIT(17)
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+
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+ #define PSYS_POWER_LIMIT2_MASK (0x1FFFFULL<<32)
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+ #define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
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+
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+ #define PSYS_TIME_WINDOW1_MASK (0x7FULL<<19)
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+ #define PSYS_TIME_WINDOW2_MASK (0x7FULL<<51)
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+
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/* Non HW constants */
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#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
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#define RAPL_PRIMITIVE_DUMMY BIT(2)
@@ -97,6 +111,7 @@ struct rapl_defaults {
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bool to_raw );
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unsigned int dram_domain_energy_unit ;
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unsigned int psys_domain_energy_unit ;
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+ bool spr_psys_bits ;
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};
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static struct rapl_defaults * rapl_defaults ;
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@@ -669,12 +684,51 @@ static struct rapl_primitive_info rpi[] = {
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RAPL_DOMAIN_REG_PERF , TIME_UNIT , 0 ),
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PRIMITIVE_INFO_INIT (PRIORITY_LEVEL , PP_POLICY_MASK , 0 ,
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RAPL_DOMAIN_REG_POLICY , ARBITRARY_UNIT , 0 ),
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+ PRIMITIVE_INFO_INIT (PSYS_POWER_LIMIT1 , PSYS_POWER_LIMIT1_MASK , 0 ,
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+ RAPL_DOMAIN_REG_LIMIT , POWER_UNIT , 0 ),
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+ PRIMITIVE_INFO_INIT (PSYS_POWER_LIMIT2 , PSYS_POWER_LIMIT2_MASK , 32 ,
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+ RAPL_DOMAIN_REG_LIMIT , POWER_UNIT , 0 ),
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+ PRIMITIVE_INFO_INIT (PSYS_PL1_ENABLE , PSYS_POWER_LIMIT1_ENABLE , 17 ,
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+ RAPL_DOMAIN_REG_LIMIT , ARBITRARY_UNIT , 0 ),
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+ PRIMITIVE_INFO_INIT (PSYS_PL2_ENABLE , PSYS_POWER_LIMIT2_ENABLE , 49 ,
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+ RAPL_DOMAIN_REG_LIMIT , ARBITRARY_UNIT , 0 ),
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+ PRIMITIVE_INFO_INIT (PSYS_TIME_WINDOW1 , PSYS_TIME_WINDOW1_MASK , 19 ,
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+ RAPL_DOMAIN_REG_LIMIT , TIME_UNIT , 0 ),
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+ PRIMITIVE_INFO_INIT (PSYS_TIME_WINDOW2 , PSYS_TIME_WINDOW2_MASK , 51 ,
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+ RAPL_DOMAIN_REG_LIMIT , TIME_UNIT , 0 ),
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/* non-hardware */
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PRIMITIVE_INFO_INIT (AVERAGE_POWER , 0 , 0 , 0 , POWER_UNIT ,
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RAPL_PRIMITIVE_DERIVED ),
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{NULL , 0 , 0 , 0 },
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};
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+ static enum rapl_primitives
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+ prim_fixups (struct rapl_domain * rd , enum rapl_primitives prim )
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+ {
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+ if (!rapl_defaults -> spr_psys_bits )
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+ return prim ;
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+
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+ if (rd -> id != RAPL_DOMAIN_PLATFORM )
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+ return prim ;
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+
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+ switch (prim ) {
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+ case POWER_LIMIT1 :
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+ return PSYS_POWER_LIMIT1 ;
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+ case POWER_LIMIT2 :
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+ return PSYS_POWER_LIMIT2 ;
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+ case PL1_ENABLE :
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+ return PSYS_PL1_ENABLE ;
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+ case PL2_ENABLE :
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+ return PSYS_PL2_ENABLE ;
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+ case TIME_WINDOW1 :
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+ return PSYS_TIME_WINDOW1 ;
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+ case TIME_WINDOW2 :
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+ return PSYS_TIME_WINDOW2 ;
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+ default :
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+ return prim ;
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+ }
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+ }
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+
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/* Read primitive data based on its related struct rapl_primitive_info.
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* if xlate flag is set, return translated data based on data units, i.e.
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* time, energy, and power.
@@ -692,7 +746,8 @@ static int rapl_read_data_raw(struct rapl_domain *rd,
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enum rapl_primitives prim , bool xlate , u64 * data )
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{
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u64 value ;
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- struct rapl_primitive_info * rp = & rpi [prim ];
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+ enum rapl_primitives prim_fixed = prim_fixups (rd , prim );
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+ struct rapl_primitive_info * rp = & rpi [prim_fixed ];
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struct reg_action ra ;
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int cpu ;
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@@ -738,7 +793,8 @@ static int rapl_write_data_raw(struct rapl_domain *rd,
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enum rapl_primitives prim ,
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unsigned long long value )
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{
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- struct rapl_primitive_info * rp = & rpi [prim ];
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+ enum rapl_primitives prim_fixed = prim_fixups (rd , prim );
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+ struct rapl_primitive_info * rp = & rpi [prim_fixed ];
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int cpu ;
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u64 bits ;
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struct reg_action ra ;
@@ -981,6 +1037,7 @@ static const struct rapl_defaults rapl_defaults_spr_server = {
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.compute_time_window = rapl_compute_time_window_core ,
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.dram_domain_energy_unit = 15300 ,
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.psys_domain_energy_unit = 1000000000 ,
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+ .spr_psys_bits = true,
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};
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static const struct rapl_defaults rapl_defaults_byt = {
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