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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/clock/samsung,exynos7870-cmu.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Samsung Exynos7870 SoC clock controller |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Kaustabh Chakraborty <kauschluss@disroot.org> |
| 11 | + |
| 12 | +description: | |
| 13 | + Exynos7870 clock controller is comprised of several CMU units, generating |
| 14 | + clocks for different domains. Those CMU units are modeled as separate device |
| 15 | + tree nodes, and might depend on each other. The root clock in that root tree |
| 16 | + is an external clock: OSCCLK (26 MHz). This external clock must be defined |
| 17 | + as a fixed-rate clock in dts. |
| 18 | +
|
| 19 | + Each clock is assigned an identifier and client nodes can use this identifier |
| 20 | + to specify the clock which they consume. All clocks available for usage |
| 21 | + in clock consumer nodes are defined as preprocessor macros in |
| 22 | + include/dt-bindings/clock/samsung,exynos7870-cmu.h header. |
| 23 | +
|
| 24 | +properties: |
| 25 | + compatible: |
| 26 | + enum: |
| 27 | + - samsung,exynos7870-cmu-mif |
| 28 | + - samsung,exynos7870-cmu-dispaud |
| 29 | + - samsung,exynos7870-cmu-fsys |
| 30 | + - samsung,exynos7870-cmu-g3d |
| 31 | + - samsung,exynos7870-cmu-isp |
| 32 | + - samsung,exynos7870-cmu-mfcmscl |
| 33 | + - samsung,exynos7870-cmu-peri |
| 34 | + |
| 35 | + clocks: |
| 36 | + minItems: 1 |
| 37 | + maxItems: 10 |
| 38 | + |
| 39 | + clock-names: |
| 40 | + minItems: 1 |
| 41 | + maxItems: 10 |
| 42 | + |
| 43 | + "#clock-cells": |
| 44 | + const: 1 |
| 45 | + |
| 46 | + reg: |
| 47 | + maxItems: 1 |
| 48 | + |
| 49 | +required: |
| 50 | + - compatible |
| 51 | + - clocks |
| 52 | + - clock-names |
| 53 | + - "#clock-cells" |
| 54 | + - reg |
| 55 | + |
| 56 | +allOf: |
| 57 | + - if: |
| 58 | + properties: |
| 59 | + compatible: |
| 60 | + contains: |
| 61 | + const: samsung,exynos7870-cmu-mif |
| 62 | + then: |
| 63 | + properties: |
| 64 | + clocks: |
| 65 | + items: |
| 66 | + - description: External reference clock (26 MHz) |
| 67 | + |
| 68 | + clock-names: |
| 69 | + items: |
| 70 | + - const: oscclk |
| 71 | + |
| 72 | + - if: |
| 73 | + properties: |
| 74 | + compatible: |
| 75 | + contains: |
| 76 | + const: samsung,exynos7870-cmu-dispaud |
| 77 | + then: |
| 78 | + properties: |
| 79 | + clocks: |
| 80 | + items: |
| 81 | + - description: External reference clock (26 MHz) |
| 82 | + - description: CMU_DISPAUD bus clock (from CMU_MIF) |
| 83 | + - description: DECON external clock (from CMU_MIF) |
| 84 | + - description: DECON vertical clock (from CMU_MIF) |
| 85 | + |
| 86 | + clock-names: |
| 87 | + items: |
| 88 | + - const: oscclk |
| 89 | + - const: bus |
| 90 | + - const: decon_eclk |
| 91 | + - const: decon_vclk |
| 92 | + |
| 93 | + - if: |
| 94 | + properties: |
| 95 | + compatible: |
| 96 | + contains: |
| 97 | + const: samsung,exynos7870-cmu-fsys |
| 98 | + then: |
| 99 | + properties: |
| 100 | + clocks: |
| 101 | + items: |
| 102 | + - description: External reference clock (26 MHz) |
| 103 | + - description: CMU_FSYS bus clock (from CMU_MIF) |
| 104 | + - description: USB20DRD clock (from CMU_MIF) |
| 105 | + |
| 106 | + clock-names: |
| 107 | + items: |
| 108 | + - const: oscclk |
| 109 | + - const: bus |
| 110 | + - const: usb20drd |
| 111 | + |
| 112 | + - if: |
| 113 | + properties: |
| 114 | + compatible: |
| 115 | + contains: |
| 116 | + const: samsung,exynos7870-cmu-g3d |
| 117 | + then: |
| 118 | + properties: |
| 119 | + clocks: |
| 120 | + items: |
| 121 | + - description: External reference clock (26 MHz) |
| 122 | + - description: G3D switch clock (from CMU_MIF) |
| 123 | + |
| 124 | + clock-names: |
| 125 | + items: |
| 126 | + - const: oscclk |
| 127 | + - const: switch |
| 128 | + |
| 129 | + - if: |
| 130 | + properties: |
| 131 | + compatible: |
| 132 | + contains: |
| 133 | + const: samsung,exynos7870-cmu-isp |
| 134 | + then: |
| 135 | + properties: |
| 136 | + clocks: |
| 137 | + items: |
| 138 | + - description: External reference clock (26 MHz) |
| 139 | + - description: ISP camera clock (from CMU_MIF) |
| 140 | + - description: ISP clock (from CMU_MIF) |
| 141 | + - description: ISP VRA clock (from CMU_MIF) |
| 142 | + |
| 143 | + clock-names: |
| 144 | + items: |
| 145 | + - const: oscclk |
| 146 | + - const: cam |
| 147 | + - const: isp |
| 148 | + - const: vra |
| 149 | + |
| 150 | + - if: |
| 151 | + properties: |
| 152 | + compatible: |
| 153 | + contains: |
| 154 | + const: samsung,exynos7870-cmu-mfcmscl |
| 155 | + then: |
| 156 | + properties: |
| 157 | + clocks: |
| 158 | + items: |
| 159 | + - description: External reference clock (26 MHz) |
| 160 | + - description: MSCL clock (from CMU_MIF) |
| 161 | + - description: MFC clock (from CMU_MIF) |
| 162 | + |
| 163 | + clock-names: |
| 164 | + items: |
| 165 | + - const: oscclk |
| 166 | + - const: mfc |
| 167 | + - const: mscl |
| 168 | + |
| 169 | + - if: |
| 170 | + properties: |
| 171 | + compatible: |
| 172 | + contains: |
| 173 | + const: samsung,exynos7870-cmu-peri |
| 174 | + then: |
| 175 | + properties: |
| 176 | + clocks: |
| 177 | + items: |
| 178 | + - description: External reference clock (26 MHz) |
| 179 | + - description: CMU_PERI bus clock (from CMU_MIF) |
| 180 | + - description: SPI0 clock (from CMU_MIF) |
| 181 | + - description: SPI1 clock (from CMU_MIF) |
| 182 | + - description: SPI2 clock (from CMU_MIF) |
| 183 | + - description: SPI3 clock (from CMU_MIF) |
| 184 | + - description: SPI4 clock (from CMU_MIF) |
| 185 | + - description: UART0 clock (from CMU_MIF) |
| 186 | + - description: UART1 clock (from CMU_MIF) |
| 187 | + - description: UART2 clock (from CMU_MIF) |
| 188 | + |
| 189 | + clock-names: |
| 190 | + items: |
| 191 | + - const: oscclk |
| 192 | + - const: bus |
| 193 | + - const: spi0 |
| 194 | + - const: spi1 |
| 195 | + - const: spi2 |
| 196 | + - const: spi3 |
| 197 | + - const: spi4 |
| 198 | + - const: uart0 |
| 199 | + - const: uart1 |
| 200 | + - const: uart2 |
| 201 | + |
| 202 | +additionalProperties: false |
| 203 | + |
| 204 | +examples: |
| 205 | + - | |
| 206 | + #include <dt-bindings/clock/samsung,exynos7870-cmu.h> |
| 207 | +
|
| 208 | + cmu_peri: clock-controller@101f0000 { |
| 209 | + compatible = "samsung,exynos7870-cmu-peri"; |
| 210 | + reg = <0x101f0000 0x1000>; |
| 211 | + #clock-cells = <1>; |
| 212 | +
|
| 213 | + clock-names = "oscclk", "bus", "spi0", "spi1", "spi2", |
| 214 | + "spi3", "spi4", "uart0", "uart1", "uart2"; |
| 215 | + clocks = <&oscclk>, |
| 216 | + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>, |
| 217 | + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>, |
| 218 | + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>, |
| 219 | + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>, |
| 220 | + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>, |
| 221 | + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>, |
| 222 | + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>, |
| 223 | + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>, |
| 224 | + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>; |
| 225 | + }; |
| 226 | +
|
| 227 | +... |
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