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Jessica Zhanglumag
Jessica Zhang
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drm/msm/dpu: Drop enable and frame_count parameters from dpu_hw_setup_misr()
Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they are always set to the same values. In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as frame_count is always set to the same value. Fixes: 7b37523 ("drm/msm/dpu: Move MISR methods to dpu_hw_util") Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/572009/ Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-2-6da6cd1bf118@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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8 files changed

+22
-33
lines changed

8 files changed

+22
-33
lines changed

‎drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
3+
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
44
* Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
55
* Copyright (C) 2013 Red Hat
66
* Author: Rob Clark <robdclark@gmail.com>
@@ -114,7 +114,7 @@ static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state)
114114
continue;
115115

116116
/* Calculate MISR over 1 frame */
117-
m->hw_lm->ops.setup_misr(m->hw_lm, true, 1);
117+
m->hw_lm->ops.setup_misr(m->hw_lm);
118118
}
119119
}
120120

‎drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
/*
33
* Copyright (C) 2013 Red Hat
44
* Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
5-
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
5+
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
66
*
77
* Author: Rob Clark <robdclark@gmail.com>
88
*/
@@ -262,7 +262,7 @@ void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc)
262262
if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr)
263263
continue;
264264

265-
phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1);
265+
phys->hw_intf->ops.setup_misr(phys->hw_intf);
266266
}
267267
}
268268

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
3+
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
44
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
55
*/
66

@@ -320,9 +320,9 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
320320
return DPU_REG_READ(c, INTF_LINE_COUNT);
321321
}
322322

323-
static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count)
323+
static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf)
324324
{
325-
dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count, 0x1);
325+
dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, 0x1);
326326
}
327327

328328
static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value)

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/* SPDX-License-Identifier: GPL-2.0-only */
22
/*
3-
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
3+
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
44
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
55
*/
66

@@ -95,7 +95,7 @@ struct dpu_hw_intf_ops {
9595

9696
void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
9797
const enum dpu_pingpong pp);
98-
void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count);
98+
void (*setup_misr)(struct dpu_hw_intf *intf);
9999
int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value);
100100

101101
// Tearcheck on INTF since DPU 5.0.0

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
3+
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
44
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
55
*/
66

@@ -83,9 +83,9 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,
8383
}
8484
}
8585

86-
static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count)
86+
static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)
8787
{
88-
dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count, 0x0);
88+
dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0);
8989
}
9090

9191
static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
/* SPDX-License-Identifier: GPL-2.0-only */
22
/*
3+
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
34
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
45
*/
56

@@ -57,7 +58,7 @@ struct dpu_hw_lm_ops {
5758
/**
5859
* setup_misr: Enable/disable MISR
5960
*/
60-
void (*setup_misr)(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count);
61+
void (*setup_misr)(struct dpu_hw_mixer *ctx);
6162

6263
/**
6364
* collect_misr: Read MISR signature

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

Lines changed: 5 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/*
3-
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
3+
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
44
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
55
*/
66
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
@@ -479,9 +479,7 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
479479
* note: Aside from encoders, input_sel should be set to 0x0 by default
480480
*/
481481
void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
482-
u32 misr_ctrl_offset,
483-
bool enable, u32 frame_count,
484-
u8 input_sel)
482+
u32 misr_ctrl_offset, u8 input_sel)
485483
{
486484
u32 config = 0;
487485

@@ -490,16 +488,9 @@ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
490488
/* Clear old MISR value (in case it's read before a new value is calculated)*/
491489
wmb();
492490

493-
if (enable) {
494-
config = (frame_count & MISR_FRAME_COUNT_MASK) |
495-
MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK |
496-
((input_sel & 0xF) << 24);
497-
498-
DPU_REG_WRITE(c, misr_ctrl_offset, config);
499-
} else {
500-
DPU_REG_WRITE(c, misr_ctrl_offset, 0);
501-
}
502-
491+
config = MISR_FRAME_COUNT | MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK |
492+
((input_sel & 0xF) << 24);
493+
DPU_REG_WRITE(c, misr_ctrl_offset, config);
503494
}
504495

505496
int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/* SPDX-License-Identifier: GPL-2.0-only */
22
/*
3-
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
3+
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
44
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
55
*/
66

@@ -13,7 +13,7 @@
1313
#include "dpu_hw_catalog.h"
1414

1515
#define REG_MASK(n) ((BIT(n)) - 1)
16-
#define MISR_FRAME_COUNT_MASK 0xFF
16+
#define MISR_FRAME_COUNT 0x1
1717
#define MISR_CTRL_ENABLE BIT(8)
1818
#define MISR_CTRL_STATUS BIT(9)
1919
#define MISR_CTRL_STATUS_CLEAR BIT(10)
@@ -361,10 +361,7 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
361361
const struct dpu_hw_qos_cfg *cfg);
362362

363363
void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
364-
u32 misr_ctrl_offset,
365-
bool enable,
366-
u32 frame_count,
367-
u8 input_sel);
364+
u32 misr_ctrl_offset, u8 input_sel);
368365

369366
int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
370367
u32 misr_ctrl_offset,

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