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BotchedRPR
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clk: samsung: exynos990: Add CMU_PERIS block
The CMU_PERIS block is used for clocking the MCT, and has one dependency clock from CMU_TOP. As the MCT is initialized early, this CMU is also registered early. While at it, make the parent clock list comment spaced out correctly, and add it to the HSI0 block. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20250104-exynos990-cmu-v1-2-9f54d69286d6@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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‎drivers/clk/samsung/clk-exynos990.c

Lines changed: 179 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
/* NOTE: Must be equal to the last clock ID increased by one */
2020
#define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1)
2121
#define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1)
22+
#define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1)
2223

2324
/* ---- CMU_TOP ------------------------------------------------------------- */
2425

@@ -449,7 +450,7 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = {
449450
PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
450451
};
451452

452-
/* Parent clock list for CMU_TOP muxes*/
453+
/* Parent clock list for CMU_TOP muxes */
453454
PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
454455
PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
455456
PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
@@ -1192,6 +1193,7 @@ static const unsigned long hsi0_clk_regs[] __initconst = {
11921193
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK,
11931194
};
11941195

1196+
/* Parent clock list for CMU_HSI0 muxes */
11951197
PNAME(mout_hsi0_bus_user_p) = { "oscclk", "dout_cmu_hsi0_bus" };
11961198
PNAME(mout_hsi0_usb31drd_user_p) = { "oscclk", "dout_cmu_hsi0_usb31drd" };
11971199
PNAME(mout_hsi0_usbdp_debug_user_p) = { "oscclk",
@@ -1305,6 +1307,182 @@ static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
13051307
.clk_name = "bus",
13061308
};
13071309

1310+
/* ---- CMU_PERIS ----------------------------------------------------------- */
1311+
1312+
/* Register Offset definitions for CMU_PERIS (0x10020000) */
1313+
#define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0600
1314+
#define PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER 0x0604
1315+
#define CLK_CON_MUX_MUX_CLK_PERIS_GIC 0x1000
1316+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x203c
1317+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK 0x204c
1318+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2048
1319+
#define CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK 0x200c
1320+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK 0x2034
1321+
#define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK 0x2010
1322+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK 0x2038
1323+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM 0x2014
1324+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2028
1325+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK 0x201c
1326+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK 0x2020
1327+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK 0x2024
1328+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2030
1329+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK 0x2018
1330+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK 0x2040
1331+
#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK 0x2044
1332+
#define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2000
1333+
#define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008
1334+
#define QCH_CON_D_TZPC_PERIS_QCH 0x3004
1335+
#define QCH_CON_GIC_QCH 0x3008
1336+
#define QCH_CON_LHM_AXI_P_PERIS_QCH 0x300c
1337+
#define QCH_CON_MCT_QCH 0x3010
1338+
#define QCH_CON_OTP_CON_BIRA_QCH 0x3014
1339+
#define QCH_CON_OTP_CON_TOP_QCH 0x301c
1340+
#define QCH_CON_PERIS_CMU_PERIS_QCH 0x3020
1341+
#define QCH_CON_SYSREG_PERIS_QCH 0x3024
1342+
#define QCH_CON_TMU_SUB_QCH 0x3028
1343+
#define QCH_CON_TMU_TOP_QCH 0x302c
1344+
#define QCH_CON_WDT_CLUSTER0_QCH 0x3030
1345+
#define QCH_CON_WDT_CLUSTER2_QCH 0x3034
1346+
1347+
static const unsigned long peris_clk_regs[] __initconst = {
1348+
PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
1349+
PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER,
1350+
CLK_CON_MUX_MUX_CLK_PERIS_GIC,
1351+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
1352+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK,
1353+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
1354+
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
1355+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
1356+
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK,
1357+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
1358+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
1359+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
1360+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
1361+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
1362+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
1363+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
1364+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
1365+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK,
1366+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
1367+
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
1368+
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
1369+
QCH_CON_D_TZPC_PERIS_QCH,
1370+
QCH_CON_GIC_QCH,
1371+
QCH_CON_LHM_AXI_P_PERIS_QCH,
1372+
QCH_CON_MCT_QCH,
1373+
QCH_CON_OTP_CON_BIRA_QCH,
1374+
QCH_CON_OTP_CON_TOP_QCH,
1375+
QCH_CON_PERIS_CMU_PERIS_QCH,
1376+
QCH_CON_SYSREG_PERIS_QCH,
1377+
QCH_CON_TMU_SUB_QCH,
1378+
QCH_CON_TMU_TOP_QCH,
1379+
QCH_CON_WDT_CLUSTER0_QCH,
1380+
QCH_CON_WDT_CLUSTER2_QCH,
1381+
};
1382+
1383+
/* Parent clock list for CMU_PERIS muxes */
1384+
PNAME(mout_peris_bus_user_p) = { "oscclk", "mout_cmu_peris_bus" };
1385+
PNAME(mout_peris_clk_peris_gic_p) = { "oscclk", "mout_peris_bus_user" };
1386+
1387+
static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
1388+
MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user",
1389+
mout_peris_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
1390+
4, 1),
1391+
MUX(CLK_MOUT_PERIS_CLK_PERIS_GIC, "mout_peris_clk_peris_gic",
1392+
mout_peris_clk_peris_gic_p, CLK_CON_MUX_MUX_CLK_PERIS_GIC,
1393+
4, 1),
1394+
};
1395+
1396+
static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1397+
GATE(CLK_GOUT_PERIS_SYSREG_PERIS_PCLK,
1398+
"gout_peris_sysreg_peris_pclk", "mout_peris_bus_user",
1399+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
1400+
21, 0, 0),
1401+
GATE(CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK,
1402+
"gout_peris_wdt_cluster2_pclk", "mout_peris_bus_user",
1403+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK,
1404+
21, 0, 0),
1405+
GATE(CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK,
1406+
"gout_peris_wdt_cluster0_pclk", "mout_peris_bus_user",
1407+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
1408+
21, 0, 0),
1409+
GATE(CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK,
1410+
"clk_peris_peris_cmu_peris_pclk", "mout_peris_bus_user",
1411+
CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
1412+
21, CLK_IGNORE_UNUSED, 0),
1413+
GATE(CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK,
1414+
"gout_peris_clk_peris_busp_clk", "mout_peris_bus_user",
1415+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
1416+
21, 0, 0),
1417+
GATE(CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK,
1418+
"gout_peris_clk_peris_oscclk_clk", "mout_peris_bus_user",
1419+
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK,
1420+
21, 0, 0),
1421+
GATE(CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK,
1422+
"gout_peris_clk_peris_gic_clk", "mout_peris_bus_user",
1423+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
1424+
21, 0, 0),
1425+
GATE(CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM,
1426+
"gout_peris_ad_axi_p_peris_aclkm", "mout_peris_bus_user",
1427+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
1428+
21, CLK_IGNORE_UNUSED, 0),
1429+
GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK,
1430+
"gout_peris_otp_con_bira_pclk", "mout_peris_bus_user",
1431+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
1432+
21, 0, 0),
1433+
GATE(CLK_GOUT_PERIS_GIC_CLK,
1434+
"gout_peris_gic_clk", "mout_peris_bus_user",
1435+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
1436+
21, CLK_IS_CRITICAL, 0),
1437+
GATE(CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK,
1438+
"gout_peris_lhm_axi_p_peris_clk", "oscclk",
1439+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
1440+
21, CLK_IGNORE_UNUSED, 0),
1441+
GATE(CLK_GOUT_PERIS_MCT_PCLK,
1442+
"gout_peris_mct_pclk", "mout_peris_clk_peris_gic",
1443+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
1444+
21, 0, 0),
1445+
GATE(CLK_GOUT_PERIS_OTP_CON_TOP_PCLK,
1446+
"gout_peris_otp_con_top_pclk", "mout_peris_clk_peris_gic",
1447+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
1448+
21, 0, 0),
1449+
GATE(CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK,
1450+
"gout_peris_d_tzpc_peris_pclk", "mout_peris_bus_user",
1451+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
1452+
21, 0, 0),
1453+
GATE(CLK_GOUT_PERIS_TMU_TOP_PCLK,
1454+
"gout_peris_tmu_top_pclk", "mout_peris_clk_peris_gic",
1455+
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
1456+
21, 0, 0),
1457+
GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK,
1458+
"gout_peris_otp_con_bira_oscclk", "oscclk",
1459+
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
1460+
21, 0, 0),
1461+
GATE(CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK,
1462+
"gout_peris_otp_con_top_oscclk", "oscclk",
1463+
CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
1464+
21, 0, 0),
1465+
};
1466+
1467+
static const struct samsung_cmu_info peris_cmu_info __initconst = {
1468+
.mux_clks = peris_mux_clks,
1469+
.nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
1470+
.gate_clks = peris_gate_clks,
1471+
.nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1472+
.nr_clk_ids = CLKS_NR_PERIS,
1473+
.clk_regs = peris_clk_regs,
1474+
.nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1475+
};
1476+
1477+
static void __init exynos990_cmu_peris_init(struct device_node *np)
1478+
{
1479+
exynos_arm64_register_cmu(NULL, np, &peris_cmu_info);
1480+
}
1481+
1482+
/* Register CMU_PERIS early, as it's a dependency for the MCT. */
1483+
CLK_OF_DECLARE(exynos990_cmu_peris, "samsung,exynos990-cmu-peris",
1484+
exynos990_cmu_peris_init);
1485+
13081486
/* ----- platform_driver ----- */
13091487

13101488
static int __init exynos990_cmu_probe(struct platform_device *pdev)

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