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17 | 17 | * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
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18 | 18 | *
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19 | 19 | * Copyright 2013 Freescale Semiconductor, Inc.
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20 |
| - * Copyright 2020 NXP |
| 20 | + * Copyright 2020, 2024 NXP |
21 | 21 | *
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22 | 22 | */
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23 | 23 |
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84 | 84 |
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85 | 85 | #define IMX_I2C_REGSHIFT 2
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86 | 86 | #define VF610_I2C_REGSHIFT 0
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| 87 | +#define S32G_I2C_REGSHIFT 0 |
87 | 88 |
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88 | 89 | /* Bits of IMX I2C registers */
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89 | 90 | #define I2SR_RXAK 0x01
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@@ -165,9 +166,34 @@ static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
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165 | 166 | { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
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166 | 167 | };
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167 | 168 |
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| 169 | +/* S32G2/S32G3 clock divider, register value pairs */ |
| 170 | +static struct imx_i2c_clk_pair s32g2_i2c_clk_div[] = { |
| 171 | + { 34, 0x00 }, { 36, 0x01 }, { 38, 0x02 }, { 40, 0x03 }, |
| 172 | + { 42, 0x04 }, { 44, 0x05 }, { 46, 0x06 }, { 48, 0x09 }, |
| 173 | + { 52, 0x0A }, { 54, 0x07 }, { 56, 0x0B }, { 60, 0x0C }, |
| 174 | + { 64, 0x0D }, { 68, 0x40 }, { 72, 0x0E }, { 76, 0x42 }, |
| 175 | + { 80, 0x12 }, { 84, 0x0F }, { 88, 0x13 }, { 96, 0x14 }, |
| 176 | + { 104, 0x15 }, { 108, 0x47 }, { 112, 0x19 }, { 120, 0x16 }, |
| 177 | + { 128, 0x1A }, { 136, 0x80 }, { 144, 0x17 }, { 152, 0x82 }, |
| 178 | + { 160, 0x1C }, { 168, 0x84 }, { 176, 0x1D }, { 192, 0x21 }, |
| 179 | + { 208, 0x1E }, { 216, 0x87 }, { 224, 0x22 }, { 240, 0x56 }, |
| 180 | + { 256, 0x1F }, { 288, 0x24 }, { 320, 0x25 }, { 336, 0x8F }, |
| 181 | + { 352, 0x93 }, { 356, 0x5D }, { 358, 0x98 }, { 384, 0x26 }, |
| 182 | + { 416, 0x56 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, |
| 183 | + { 576, 0x2C }, { 640, 0x2D }, { 704, 0x9D }, { 768, 0x2E }, |
| 184 | + { 832, 0x9D }, { 896, 0x32 }, { 960, 0x2F }, { 1024, 0x33 }, |
| 185 | + { 1152, 0x34 }, { 1280, 0x35 }, { 1536, 0x36 }, { 1792, 0x3A }, |
| 186 | + { 1920, 0x37 }, { 2048, 0x3B }, { 2304, 0x74 }, { 2560, 0x3D }, |
| 187 | + { 3072, 0x3E }, { 3584, 0x7A }, { 3840, 0x3F }, { 4096, 0x7B }, |
| 188 | + { 4608, 0x7C }, { 5120, 0x7D }, { 6144, 0x7E }, { 7168, 0xBA }, |
| 189 | + { 7680, 0x7F }, { 8192, 0xBB }, { 9216, 0xBC }, { 10240, 0xBD }, |
| 190 | + { 12288, 0xBE }, { 15360, 0xBF }, |
| 191 | +}; |
| 192 | + |
168 | 193 | enum imx_i2c_type {
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169 | 194 | IMX1_I2C,
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170 | 195 | IMX21_I2C,
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| 196 | + S32G_I2C, |
171 | 197 | VF610_I2C,
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172 | 198 | };
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173 | 199 |
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@@ -277,7 +303,15 @@ static struct imx_i2c_hwdata vf610_i2c_hwdata = {
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277 | 303 | .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
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278 | 304 | .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
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279 | 305 | .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
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| 306 | +}; |
280 | 307 |
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| 308 | +static const struct imx_i2c_hwdata s32g2_i2c_hwdata = { |
| 309 | + .devtype = S32G_I2C, |
| 310 | + .regshift = S32G_I2C_REGSHIFT, |
| 311 | + .clk_div = s32g2_i2c_clk_div, |
| 312 | + .ndivs = ARRAY_SIZE(s32g2_i2c_clk_div), |
| 313 | + .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, |
| 314 | + .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, |
281 | 315 | };
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282 | 316 |
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283 | 317 | static const struct platform_device_id imx_i2c_devtype[] = {
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@@ -307,6 +341,7 @@ static const struct of_device_id i2c_imx_dt_ids[] = {
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307 | 341 | { .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, },
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308 | 342 | { .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, },
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309 | 343 | { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
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| 344 | + { .compatible = "nxp,s32g2-i2c", .data = &s32g2_i2c_hwdata, }, |
310 | 345 | { /* sentinel */ }
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311 | 346 | };
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312 | 347 | MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
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