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Merge tag 'counter-fixes-for-6.14' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/wbg/counter into char-misc-linus
William writes: Counter fixes for 6.14 A fix to resolve a timeout error during counter enable leading to a false report of 'enable' state in stm32-lptimer-cnt. A fix to properly intialize counter channels during probe to avoid operating under an undefined state in microchip-tcb-capture. * tag 'counter-fixes-for-6.14' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/wbg/counter: counter: microchip-tcb-capture: Fix undefined counter channel state on probe counter: stm32-lptimer-cnt: fix error handling when enabling
2 parents 80e54e8 + c0c9c73 commit 2dc2509

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2 files changed

+34
-9
lines changed

2 files changed

+34
-9
lines changed

drivers/counter/microchip-tcb-capture.c

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -368,6 +368,25 @@ static int mchp_tc_probe(struct platform_device *pdev)
368368
channel);
369369
}
370370

371+
/* Disable Quadrature Decoder and position measure */
372+
ret = regmap_update_bits(regmap, ATMEL_TC_BMR, ATMEL_TC_QDEN | ATMEL_TC_POSEN, 0);
373+
if (ret)
374+
return ret;
375+
376+
/* Setup the period capture mode */
377+
ret = regmap_update_bits(regmap, ATMEL_TC_REG(priv->channel[0], CMR),
378+
ATMEL_TC_WAVE | ATMEL_TC_ABETRG | ATMEL_TC_CMR_MASK |
379+
ATMEL_TC_TCCLKS,
380+
ATMEL_TC_CMR_MASK);
381+
if (ret)
382+
return ret;
383+
384+
/* Enable clock and trigger counter */
385+
ret = regmap_write(regmap, ATMEL_TC_REG(priv->channel[0], CCR),
386+
ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
387+
if (ret)
388+
return ret;
389+
371390
priv->tc_cfg = tcb_config;
372391
priv->regmap = regmap;
373392
counter->name = dev_name(&pdev->dev);

drivers/counter/stm32-lptimer-cnt.c

Lines changed: 15 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -58,37 +58,43 @@ static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv,
5858
return 0;
5959
}
6060

61+
ret = clk_enable(priv->clk);
62+
if (ret)
63+
goto disable_cnt;
64+
6165
/* LP timer must be enabled before writing CMP & ARR */
6266
ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
6367
if (ret)
64-
return ret;
68+
goto disable_clk;
6569

6670
ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
6771
if (ret)
68-
return ret;
72+
goto disable_clk;
6973

7074
/* ensure CMP & ARR registers are properly written */
7175
ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
7276
(val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK,
7377
100, 1000);
7478
if (ret)
75-
return ret;
79+
goto disable_clk;
7680

7781
ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
7882
STM32_LPTIM_CMPOKCF_ARROKCF);
7983
if (ret)
80-
return ret;
84+
goto disable_clk;
8185

82-
ret = clk_enable(priv->clk);
83-
if (ret) {
84-
regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
85-
return ret;
86-
}
8786
priv->enabled = true;
8887

8988
/* Start LP timer in continuous mode */
9089
return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
9190
STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
91+
92+
disable_clk:
93+
clk_disable(priv->clk);
94+
disable_cnt:
95+
regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
96+
97+
return ret;
9298
}
9399

94100
static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)

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