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Merge tag 'dmaengine-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul: "This time we have bunch of driver updates and some new device support. New support: - Document RZ/V2L and RZ/G2UL dma binding - TI AM62x k3-udma and k3-psil support Updates: - Yaml conversion for Mediatek uart apdma schema - Removal of DMA-32 fallback configuration for various drivers - imx-sdma updates for channel restart" * tag 'dmaengine-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (23 commits) dmaengine: hisi_dma: fix MSI allocate fail when reload hisi_dma dmaengine: dw-axi-dmac: cleanup comments dmaengine: fsl-dpaa2-qdma: Drop comma after SoC match table sentinel dt-bindings: dma: Convert mtk-uart-apdma to DT schema dmaengine: ppc4xx: Make use of the helper macro LIST_HEAD() dmaengine: idxd: Remove useless DMA-32 fallback configuration dmaengine: qcom_hidma: Remove useless DMA-32 fallback configuration dmaengine: sh: Kconfig: Add ARCH_R9A07G054 dependency for RZ_DMAC config option dmaengine: ti: k3-psil: Add AM62x PSIL and PDMA data dmaengine: ti: k3-udma: Add AM62x DMSS support dmaengine: ti: cleanup comments dmaengine: imx-sdma: clean up some inconsistent indenting dmaengine: Revert "dmaengine: shdma: Fix runtime PM imbalance on error" dmaengine: idxd: restore traffic class defaults after wq reset dmaengine: altera-msgdma: Remove useless DMA-32 fallback configuration dmaengine: stm32-dma: set dma_device max_sg_burst dmaengine: imx-sdma: fix cyclic buffer race condition dmaengine: imx-sdma: restart cyclic channel if needed dmaengine: iot: Remove useless DMA-32 fallback configuration dmaengine: ptdma: handle the cases based on DMA is complete ...
2 parents 2c54e18 + b95044b commit 2a44cda

26 files changed

+383
-103
lines changed

‎Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml

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@@ -0,0 +1,122 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
3+
---
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$id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
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7+
title: MediaTek UART APDMA controller
8+
9+
maintainers:
10+
- Long Cheng <long.cheng@mediatek.com>
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12+
description: |
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The MediaTek UART APDMA controller provides DMA capabilities
14+
for the UART peripheral bus.
15+
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allOf:
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- $ref: "dma-controller.yaml#"
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- mediatek,mt2712-uart-dma
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- mediatek,mt8516-uart-dma
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- const: mediatek,mt6577-uart-dma
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- enum:
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- mediatek,mt6577-uart-dma
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reg:
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minItems: 1
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maxItems: 16
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interrupts:
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description: |
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TX, RX interrupt lines for each UART APDMA channel
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minItems: 1
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maxItems: 16
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clocks:
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description: Must contain one entry for the APDMA main clock
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maxItems: 1
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clock-names:
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const: apdma
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"#dma-cells":
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const: 1
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description: |
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The first cell specifies the UART APDMA channel number
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dma-requests:
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description: |
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Number of virtual channels of the UART APDMA controller
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maximum: 16
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mediatek,dma-33bits:
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type: boolean
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description: Enable 33-bits UART APDMA support
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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if:
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not:
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required:
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- dma-requests
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then:
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properties:
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interrupts:
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maxItems: 8
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reg:
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maxItems: 8
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt2712-clk.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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apdma: dma-controller@11000400 {
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compatible = "mediatek,mt2712-uart-dma",
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"mediatek,mt6577-uart-dma";
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reg = <0 0x11000400 0 0x80>,
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<0 0x11000480 0 0x80>,
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<0 0x11000500 0 0x80>,
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<0 0x11000580 0 0x80>,
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<0 0x11000600 0 0x80>,
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<0 0x11000680 0 0x80>,
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<0 0x11000700 0 0x80>,
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<0 0x11000780 0 0x80>,
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<0 0x11000800 0 0x80>,
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<0 0x11000880 0 0x80>,
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<0 0x11000900 0 0x80>,
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<0 0x11000980 0 0x80>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
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dma-requests = <12>;
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clocks = <&pericfg CLK_PERI_AP_DMA>;
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clock-names = "apdma";
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mediatek,dma-33bits;
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#dma-cells = <1>;
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};
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};
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...

‎Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt

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This file was deleted.

‎Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml

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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
55
$schema: http://devicetree.org/meta-schemas/core.yaml#
66

7-
title: Renesas RZ/G2L DMA Controller
7+
title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
88

99
maintainers:
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- Biju Das <biju.das.jz@bp.renesas.com>
@@ -16,7 +16,9 @@ properties:
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compatible:
1717
items:
1818
- enum:
19+
- renesas,r9a07g043-dmac # RZ/G2UL
1920
- renesas,r9a07g044-dmac # RZ/G2{L,LC}
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- renesas,r9a07g054-dmac # RZ/V2L
2022
- const: renesas,rz-dmac
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2224
reg:

‎drivers/dma/altera-msgdma.c

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@@ -891,9 +891,7 @@ static int msgdma_probe(struct platform_device *pdev)
891891
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
892892
if (ret) {
893893
dev_warn(&pdev->dev, "unable to set coherent mask to 64");
894-
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
895-
if (ret)
896-
goto fail;
894+
goto fail;
897895
}
898896

899897
msgdma_reset(mdev);

‎drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c

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@@ -1,4 +1,4 @@
1-
// SPDX-License-Identifier: GPL-2.0
1+
// SPDX-License-Identifier: GPL-2.0
22
// (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
33

44
/*
@@ -35,7 +35,7 @@
3535
/*
3636
* The set of bus widths supported by the DMA controller. DW AXI DMAC supports
3737
* master data bus width up to 512 bits (for both AXI master interfaces), but
38-
* it depends on IP block configurarion.
38+
* it depends on IP block configuration.
3939
*/
4040
#define AXI_DMA_BUSWIDTHS \
4141
(DMA_SLAVE_BUSWIDTH_1_BYTE | \
@@ -1089,10 +1089,10 @@ static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id)
10891089

10901090
u32 status, i;
10911091

1092-
/* Disable DMAC inerrupts. We'll enable them after processing chanels */
1092+
/* Disable DMAC interrupts. We'll enable them after processing channels */
10931093
axi_dma_irq_disable(chip);
10941094

1095-
/* Poll, clear and process every chanel interrupt status */
1095+
/* Poll, clear and process every channel interrupt status */
10961096
for (i = 0; i < dw->hdata->nr_channels; i++) {
10971097
chan = &dw->chan[i];
10981098
status = axi_chan_irq_read(chan);

‎drivers/dma/dw-axi-dmac/dw-axi-dmac.h

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@@ -1,4 +1,4 @@
1-
// SPDX-License-Identifier: GPL-2.0
1+
/* SPDX-License-Identifier: GPL-2.0 */
22
// (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
33

44
/*

‎drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h

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@@ -139,7 +139,7 @@ struct dpaa2_qdma_priv_per_prio {
139139

140140
static struct soc_device_attribute soc_fixup_tuning[] = {
141141
{ .family = "QorIQ LX2160A"},
142-
{ },
142+
{ /* sentinel */ }
143143
};
144144

145145
/* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */

‎drivers/dma/hisi_dma.c

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@@ -30,7 +30,7 @@
3030
#define HISI_DMA_MODE 0x217c
3131
#define HISI_DMA_OFFSET 0x100
3232

33-
#define HISI_DMA_MSI_NUM 30
33+
#define HISI_DMA_MSI_NUM 32
3434
#define HISI_DMA_CHAN_NUM 30
3535
#define HISI_DMA_Q_DEPTH_VAL 1024
3636

‎drivers/dma/idxd/device.c

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -681,8 +681,13 @@ static void idxd_groups_clear_state(struct idxd_device *idxd)
681681
group->use_rdbuf_limit = false;
682682
group->rdbufs_allowed = 0;
683683
group->rdbufs_reserved = 0;
684-
group->tc_a = -1;
685-
group->tc_b = -1;
684+
if (idxd->hw.version < DEVICE_VERSION_2 && !tc_override) {
685+
group->tc_a = 1;
686+
group->tc_b = 1;
687+
} else {
688+
group->tc_a = -1;
689+
group->tc_b = -1;
690+
}
686691
}
687692
}
688693

‎drivers/dma/idxd/init.c

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@@ -604,8 +604,6 @@ static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
604604

605605
dev_dbg(dev, "Set DMA masks\n");
606606
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
607-
if (rc)
608-
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
609607
if (rc)
610608
goto err;
611609

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