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Merge tag 'char-misc-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc and other driver updates from Greg KH: "Here is the big set of char/misc and other driver subsystem changes for 6.8-rc1. Other than lots of binder driver changes (as you can see by the merge conflicts) included in here are: - lots of iio driver updates and additions - spmi driver updates - eeprom driver updates - firmware driver updates - ocxl driver updates - mhi driver updates - w1 driver updates - nvmem driver updates - coresight driver updates - platform driver remove callback api changes - tags.sh script updates - bus_type constant marking cleanups - lots of other small driver updates All of these have been in linux-next for a while with no reported issues" * tag 'char-misc-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (341 commits) android: removed duplicate linux/errno uio: Fix use-after-free in uio_open drivers: soc: xilinx: add check for platform firmware: xilinx: Export function to use in other module scripts/tags.sh: remove find_sources scripts/tags.sh: use -n to test archinclude scripts/tags.sh: add local annotation scripts/tags.sh: use more portable -path instead of -wholename scripts/tags.sh: Update comment (addition of gtags) firmware: zynqmp: Convert to platform remove callback returning void firmware: turris-mox-rwtm: Convert to platform remove callback returning void firmware: stratix10-svc: Convert to platform remove callback returning void firmware: stratix10-rsu: Convert to platform remove callback returning void firmware: raspberrypi: Convert to platform remove callback returning void firmware: qemu_fw_cfg: Convert to platform remove callback returning void firmware: mtk-adsp-ipc: Convert to platform remove callback returning void firmware: imx-dsp: Convert to platform remove callback returning void firmware: coreboot_table: Convert to platform remove callback returning void firmware: arm_scpi: Convert to platform remove callback returning void firmware: arm_scmi: Convert to platform remove callback returning void ...
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‎.mailmap

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@@ -390,9 +390,10 @@ Matthias Fuchs <socketcan@esd.eu> <matthias.fuchs@esd.eu>
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Matthieu Baerts <matttbe@kernel.org> <matthieu.baerts@tessares.net>
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Matthieu CASTET <castet.matthieu@free.fr>
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Matti Vaittinen <mazziesaccount@gmail.com> <matti.vaittinen@fi.rohmeurope.com>
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Matt Ranostay <matt.ranostay@konsulko.com> <matt@ranostay.consulting>
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Matt Ranostay <mranostay@gmail.com> Matthew Ranostay <mranostay@embeddedalley.com>
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Matt Ranostay <mranostay@gmail.com> <matt.ranostay@intel.com>
393+
Matt Ranostay <matt@ranostay.sg> <matt.ranostay@konsulko.com>
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Matt Ranostay <matt@ranostay.sg> <matt@ranostay.consulting>
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Matt Ranostay <matt@ranostay.sg> Matthew Ranostay <mranostay@embeddedalley.com>
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Matt Ranostay <matt@ranostay.sg> <matt.ranostay@intel.com>
396397
Matt Redfearn <matt.redfearn@mips.com> <matt.redfearn@imgtec.com>
397398
Maulik Shah <quic_mkshah@quicinc.com> <mkshah@codeaurora.org>
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Mauro Carvalho Chehab <mchehab@kernel.org> <maurochehab@gmail.com>

‎Documentation/ABI/testing/sysfs-bus-cdx

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@@ -98,6 +98,13 @@ Description:
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# echo 1 > /sys/bus/cdx/devices/.../remove
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What: /sys/bus/cdx/devices/.../resource<N>
102+
Date: July 2023
103+
Contact: puneet.gupta@amd.com
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Description:
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The resource binary file contains the content of the memory
106+
regions. These files can be m'maped from userspace.
107+
101108
What: /sys/bus/cdx/devices/.../modalias
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Date: July 2023
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Contact: nipun.gupta@amd.com

‎Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc

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Original file line numberDiff line numberDiff line change
@@ -91,3 +91,19 @@ Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Size of the trace buffer for TMC-ETR when used in SYSFS
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mode. Writable only for TMC-ETR configurations. The value
9393
should be aligned to the kernel pagesize.
94+
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What: /sys/bus/coresight/devices/<memory_map>.tmc/buf_modes_available
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Date: August 2023
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KernelVersion: 6.7
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Contact: Anshuman Khandual <anshuman.khandual@arm.com>
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Description: (Read) Shows all supported Coresight TMC-ETR buffer modes available
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for the users to configure explicitly. This file is avaialble only
101+
for TMC ETR devices.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/buf_mode_preferred
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Date: August 2023
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KernelVersion: 6.7
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Contact: Anshuman Khandual <anshuman.khandual@arm.com>
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Description: (RW) Current Coresight TMC-ETR buffer mode selected. But user could
108+
only provide a mode which is supported for a given ETR device. This
109+
file is available only for TMC ETR devices.

‎Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm

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Original file line numberDiff line numberDiff line change
@@ -11,3 +11,162 @@ Description:
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Accepts only one of the 2 values - 1 or 2.
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1 : Generate 64 bits data
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2 : Generate 32 bits data
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What: /sys/bus/coresight/devices/<tpdm-name>/reset_dataset
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(Write) Reset the dataset of the tpdm.
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Accepts only one value - 1.
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1 : Reset the dataset of the tpdm
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the trigger type of the DSB for tpdm.
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Accepts only one of the 2 values - 0 or 1.
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0 : Set the DSB trigger type to false
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1 : Set the DSB trigger type to true
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the trigger timestamp of the DSB for tpdm.
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Accepts only one of the 2 values - 0 or 1.
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0 : Set the DSB trigger type to false
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1 : Set the DSB trigger type to true
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_mode
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the programming mode of the DSB for tpdm.
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Accepts the value needs to be greater than 0. What data
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bits do is listed below.
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Bit[0:1] : Test mode control bit for choosing the inputs.
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Bit[3] : Set to 0 for low performance mode. Set to 1 for high
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performance mode.
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Bit[4:8] : Select byte lane for high performance mode.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the index number of the edge detection for the DSB
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subunit TPDM. Since there are at most 256 edge detections, this
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value ranges from 0 to 255.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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Write a data to control the edge detection corresponding to
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the index number. Before writing data to this sysfs file,
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"ctrl_idx" should be written first to configure the index
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number of the edge detection which needs to be controlled.
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Accepts only one of the following values.
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0 - Rising edge detection
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1 - Falling edge detection
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2 - Rising and falling edge detection (toggle detection)
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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Write a data to mask the edge detection corresponding to the index
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number. Before writing data to this sysfs file, "ctrl_idx" should
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be written first to configure the index number of the edge detection
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which needs to be masked.
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Accepts only one of the 2 values - 0 or 1.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15]
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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Read a set of the edge control value of the DSB in TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7]
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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Read a set of the edge control mask of the DSB in TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7]
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the value of the trigger pattern for the DSB
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subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7]
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the mask of the trigger pattern for the DSB
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subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7]
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the value of the pattern for the DSB subunit TPDM.
134+
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7]
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
140+
(RW) Set/Get the mask of the pattern for the DSB subunit TPDM.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts
143+
Date: March 2023
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KernelVersion 6.7
145+
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
146+
Description:
147+
(Write) Set the pattern timestamp of DSB tpdm. Read
148+
the pattern timestamp of DSB tpdm.
149+
150+
Accepts only one of the 2 values - 0 or 1.
151+
0 : Disable DSB pattern timestamp.
152+
1 : Enable DSB pattern timestamp.
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154+
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type
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Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(Write) Set the pattern type of DSB tpdm. Read
160+
the pattern type of DSB tpdm.
161+
162+
Accepts only one of the 2 values - 0 or 1.
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0 : Set the DSB pattern type to value.
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1 : Set the DSB pattern type to toggle.
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31]
167+
Date: March 2023
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KernelVersion 6.7
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Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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Description:
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(RW) Set/Get the MSR(mux select register) for the DSB subunit
172+
TPDM.

‎Documentation/ABI/testing/sysfs-bus-iio

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Original file line numberDiff line numberDiff line change
@@ -362,10 +362,21 @@ Description:
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What: /sys/bus/iio/devices/iio:deviceX/in_accel_x_peak_raw
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What: /sys/bus/iio/devices/iio:deviceX/in_accel_y_peak_raw
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What: /sys/bus/iio/devices/iio:deviceX/in_accel_z_peak_raw
365+
What: /sys/bus/iio/devices/iio:deviceX/in_humidityrelative_peak_raw
366+
What: /sys/bus/iio/devices/iio:deviceX/in_temp_peak_raw
365367
KernelVersion: 2.6.36
366368
Contact: linux-iio@vger.kernel.org
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Description:
368-
Highest value since some reset condition. These
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Highest value since some reset condition. These
371+
attributes allow access to this and are otherwise
372+
the direct equivalent of the <type>Y[_name]_raw attributes.
373+
374+
What: /sys/bus/iio/devices/iio:deviceX/in_humidityrelative_trough_raw
375+
What: /sys/bus/iio/devices/iio:deviceX/in_temp_trough_raw
376+
KernelVersion: 6.7
377+
Contact: linux-iio@vger.kernel.org
378+
Description:
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Lowest value since some reset condition. These
369380
attributes allow access to this and are otherwise
370381
the direct equivalent of the <type>Y[_name]_raw attributes.
371382

@@ -618,7 +629,9 @@ KernelVersion: 2.6.35
618629
Contact: linux-iio@vger.kernel.org
619630
Description:
620631
If a discrete set of scale values is available, they
621-
are listed in this attribute.
632+
are listed in this attribute. Unlike illumination,
633+
multiplying intensity by intensity_scale does not
634+
yield value with any standardized unit.
622635

623636
What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_hardwaregain
624637
What: /sys/bus/iio/devices/iio:deviceX/in_intensity_hardwaregain
@@ -1574,6 +1587,8 @@ What: /sys/.../iio:deviceX/in_intensityY_raw
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What: /sys/.../iio:deviceX/in_intensityY_ir_raw
15751588
What: /sys/.../iio:deviceX/in_intensityY_both_raw
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What: /sys/.../iio:deviceX/in_intensityY_uv_raw
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What: /sys/.../iio:deviceX/in_intensityY_uva_raw
1591+
What: /sys/.../iio:deviceX/in_intensityY_uvb_raw
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What: /sys/.../iio:deviceX/in_intensityY_duv_raw
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KernelVersion: 3.4
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Contact: linux-iio@vger.kernel.org
@@ -1582,8 +1597,9 @@ Description:
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that measurements contain visible and infrared light
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components or just infrared light, respectively. Modifier
15841599
uv indicates that measurements contain ultraviolet light
1585-
components. Modifier duv indicates that measurements
1586-
contain deep ultraviolet light components.
1600+
components. Modifiers uva, uvb and duv indicate that
1601+
measurements contain A, B or deep (C) ultraviolet light
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components respectively.
15871603

15881604
What: /sys/.../iio:deviceX/in_uvindex_input
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KernelVersion: 4.6
@@ -2254,3 +2270,21 @@ Description:
22542270
If a label is defined for this event add that to the event
22552271
specific attributes. This is useful for userspace to be able to
22562272
better identify an individual event.
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2274+
What: /sys/.../events/in_accel_gesture_tap_wait_timeout
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KernelVersion: 6.7
2276+
Contact: linux-iio@vger.kernel.org
2277+
Description:
2278+
Enable tap gesture confirmation with timeout.
2279+
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What: /sys/.../events/in_accel_gesture_tap_wait_dur
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KernelVersion: 6.7
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Contact: linux-iio@vger.kernel.org
2283+
Description:
2284+
Timeout value in seconds for tap gesture confirmation.
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What: /sys/.../events/in_accel_gesture_tap_wait_dur_available
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KernelVersion: 6.7
2288+
Contact: linux-iio@vger.kernel.org
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Description:
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List of available timeout value for tap gesture confirmation.

‎Documentation/ABI/testing/sysfs-nvmem-cells

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
What: /sys/bus/nvmem/devices/.../cells/<cell-name>
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Date: May 2023
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KernelVersion: 6.5
4+
Contact: Miquel Raynal <miquel.raynal@bootlin.com>
5+
Description:
6+
The "cells" folder contains one file per cell exposed by the
7+
NVMEM device. The name of the file is: <name>@<where>, with
8+
<name> being the cell name and <where> its location in the NVMEM
9+
device, in hexadecimal (without the '0x' prefix, to mimic device
10+
tree node names). The length of the file is the size of the cell
11+
(when known). The content of the file is the binary content of
12+
the cell (may sometimes be ASCII, likely without trailing
13+
character).
14+
Note: This file is only present if CONFIG_NVMEM_SYSFS
15+
is enabled.
16+
17+
Example::
18+
19+
hexdump -C /sys/bus/nvmem/devices/1-00563/cells/product-name@d
20+
00000000 54 4e 34 38 4d 2d 50 2d 44 4e |TN48M-P-DN|
21+
0000000a

‎Documentation/arch/arm64/silicon-errata.rst

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@@ -117,6 +117,10 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
118118
| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
119119
+----------------+-----------------+-----------------+-----------------------------+
120+
| ARM | Cortex-A76 | #1490853 | N/A |
121+
+----------------+-----------------+-----------------+-----------------------------+
122+
| ARM | Cortex-A77 | #1491015 | N/A |
123+
+----------------+-----------------+-----------------+-----------------------------+
120124
| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
121125
+----------------+-----------------+-----------------+-----------------------------+
122126
| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
@@ -127,6 +131,8 @@ stable kernels.
127131
+----------------+-----------------+-----------------+-----------------------------+
128132
| ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 |
129133
+----------------+-----------------+-----------------+-----------------------------+
134+
| ARM | Cortex-X1 | #1502854 | N/A |
135+
+----------------+-----------------+-----------------+-----------------------------+
130136
| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
131137
+----------------+-----------------+-----------------+-----------------------------+
132138
| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
@@ -135,6 +141,8 @@ stable kernels.
135141
+----------------+-----------------+-----------------+-----------------------------+
136142
| ARM | Neoverse-N1 | #1349291 | N/A |
137143
+----------------+-----------------+-----------------+-----------------------------+
144+
| ARM | Neoverse-N1 | #1490853 | N/A |
145+
+----------------+-----------------+-----------------+-----------------------------+
138146
| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
139147
+----------------+-----------------+-----------------+-----------------------------+
140148
| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
@@ -143,6 +151,8 @@ stable kernels.
143151
+----------------+-----------------+-----------------+-----------------------------+
144152
| ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 |
145153
+----------------+-----------------+-----------------+-----------------------------+
154+
| ARM | Neoverse-V1 | #1619801 | N/A |
155+
+----------------+-----------------+-----------------+-----------------------------+
146156
| ARM | MMU-500 | #841119,826419 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | MMU-600 | #1076982,1209401| N/A |

‎Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml

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Original file line numberDiff line numberDiff line change
@@ -44,6 +44,23 @@ properties:
4444
minItems: 1
4545
maxItems: 2
4646

47+
qcom,dsb-element-size:
48+
description:
49+
Specifies the DSB(Discrete Single Bit) element size supported by
50+
the monitor. The associated aggregator will read this size before it
51+
is enabled. DSB element size currently only supports 32-bit and 64-bit.
52+
$ref: /schemas/types.yaml#/definitions/uint8
53+
enum: [32, 64]
54+
55+
qcom,dsb-msrs-num:
56+
description:
57+
Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)
58+
registers supported by the monitor. If this property is not configured
59+
or set to 0, it means this DSB TPDM doesn't support MSR.
60+
$ref: /schemas/types.yaml#/definitions/uint32
61+
minimum: 0
62+
maximum: 32
63+
4764
clocks:
4865
maxItems: 1
4966

@@ -77,6 +94,9 @@ examples:
7794
compatible = "qcom,coresight-tpdm", "arm,primecell";
7895
reg = <0x0684c000 0x1000>;
7996
97+
qcom,dsb-element-size = /bits/ 8 <32>;
98+
qcom,dsb-msrs-num = <16>;
99+
80100
clocks = <&aoss_qmp>;
81101
clock-names = "apb_pclk";
82102

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