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cxl/events: Update DRAM Event Record to CXL spec rev 3.1
CXL spec 3.1 section 8.2.9.2.1.2 Table 8-46, DRAM Event Record has updated with following new fields and new types for Memory Event Type, Transaction Type and Validity Flags fields. 1. Component Identifier 2. Sub-channel 3. Advanced Programmable Corrected Memory Error Threshold Event Flags 4. Corrected Memory Error Count at Event 5. Memory Event Sub-Type Update DRAM events record and DRAM trace event for the above spec changes. The new fields are inserted in logical places. Includes trivial consistency of white space improvements. Example trace print of cxl_dram trace event, cxl_dram: memdev=mem0 host=0000:0f:00.0 serial=3 log=Informational : \ time=54799339519 uuid=601dcbb3-9c06-4eab-b8af-4e9bfb5c9624 len=128 \ flags='0x1' handle=1 related_handle=0 maint_op_class=1 \ maint_op_sub_class=3 : dpa=18680 dpa_flags='' \ descriptor='UNCORRECTABLE_EVENT|THRESHOLD_EVENT' type='Data Path Error' \ sub_type='Media Link CRC Error' transaction_type='Internal Media Scrub' \ channel=3 rank=17 nibble_mask=3b00b2 bank_group=7 bank=11 row=2 \ column=77 cor_mask=21 00 00 00 00 00 00 00 2c 00 00 00 00 00 00 00 37 00 \ 00 00 00 00 00 00 42 00 00 00 00 00 00 00 validity_flags='CHANNEL|RANK|NIBBLE|\ BANK GROUP|BANK|ROW|COLUMN|CORRECTION MASK|COMPONENT|COMPONENT PLDM FORMAT' \ comp_id=01 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \ comp_id_pldm_valid_flags='PLDM Entity ID' pldm_entity_id=74 c5 08 9a 1a 0b \ pldm_resource_id=0x00 hpa=ffffffffffffffff region= \ region_uuid=00000000-0000-0000-0000-000000000000 sub_channel=5 \ cme_threshold_ev_flags='Corrected Memory Errors in Multiple Media Components|\ Exceeded Programmable Threshold' cvme_count=148 Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Link: https://patch.msgid.link/20250111091756.1682-5-shiju.jose@huawei.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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‎drivers/cxl/core/trace.h

Lines changed: 54 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -478,7 +478,7 @@ TRACE_EVENT(cxl_general_media,
478478
/*
479479
* DRAM Event Record - DER
480480
*
481-
* CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44
481+
* CXL rev 3.1 section 8.2.9.2.1.2; Table 8-46
482482
*/
483483
/*
484484
* DRAM Event Record defines many fields the same as the General Media Event
@@ -488,11 +488,17 @@ TRACE_EVENT(cxl_general_media,
488488
#define CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR 0x01
489489
#define CXL_DER_MEM_EVT_TYPE_INV_ADDR 0x02
490490
#define CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR 0x03
491-
#define show_dram_mem_event_type(type) __print_symbolic(type, \
492-
{ CXL_DER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \
493-
{ CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR, "Scrub Media ECC Error" }, \
494-
{ CXL_DER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \
495-
{ CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" } \
491+
#define CXL_DER_MEM_EVT_TYPE_TE_STATE_VIOLATION 0x04
492+
#define CXL_DER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE 0x05
493+
#define CXL_DER_MEM_EVT_TYPE_CKID_VIOLATION 0x06
494+
#define show_dram_mem_event_type(type) __print_symbolic(type, \
495+
{ CXL_DER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \
496+
{ CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR, "Scrub Media ECC Error" }, \
497+
{ CXL_DER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \
498+
{ CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" }, \
499+
{ CXL_DER_MEM_EVT_TYPE_TE_STATE_VIOLATION, "TE State Violation" }, \
500+
{ CXL_DER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE, "Adv Prog CME Counter Expiration" }, \
501+
{ CXL_DER_MEM_EVT_TYPE_CKID_VIOLATION, "CKID Violation" } \
496502
)
497503

498504
#define CXL_DER_VALID_CHANNEL BIT(0)
@@ -503,15 +509,21 @@ TRACE_EVENT(cxl_general_media,
503509
#define CXL_DER_VALID_ROW BIT(5)
504510
#define CXL_DER_VALID_COLUMN BIT(6)
505511
#define CXL_DER_VALID_CORRECTION_MASK BIT(7)
506-
#define show_dram_valid_flags(flags) __print_flags(flags, "|", \
507-
{ CXL_DER_VALID_CHANNEL, "CHANNEL" }, \
508-
{ CXL_DER_VALID_RANK, "RANK" }, \
509-
{ CXL_DER_VALID_NIBBLE, "NIBBLE" }, \
510-
{ CXL_DER_VALID_BANK_GROUP, "BANK GROUP" }, \
511-
{ CXL_DER_VALID_BANK, "BANK" }, \
512-
{ CXL_DER_VALID_ROW, "ROW" }, \
513-
{ CXL_DER_VALID_COLUMN, "COLUMN" }, \
514-
{ CXL_DER_VALID_CORRECTION_MASK, "CORRECTION MASK" } \
512+
#define CXL_DER_VALID_COMPONENT BIT(8)
513+
#define CXL_DER_VALID_COMPONENT_ID_FORMAT BIT(9)
514+
#define CXL_DER_VALID_SUB_CHANNEL BIT(10)
515+
#define show_dram_valid_flags(flags) __print_flags(flags, "|", \
516+
{ CXL_DER_VALID_CHANNEL, "CHANNEL" }, \
517+
{ CXL_DER_VALID_RANK, "RANK" }, \
518+
{ CXL_DER_VALID_NIBBLE, "NIBBLE" }, \
519+
{ CXL_DER_VALID_BANK_GROUP, "BANK GROUP" }, \
520+
{ CXL_DER_VALID_BANK, "BANK" }, \
521+
{ CXL_DER_VALID_ROW, "ROW" }, \
522+
{ CXL_DER_VALID_COLUMN, "COLUMN" }, \
523+
{ CXL_DER_VALID_CORRECTION_MASK, "CORRECTION MASK" }, \
524+
{ CXL_DER_VALID_COMPONENT, "COMPONENT" }, \
525+
{ CXL_DER_VALID_COMPONENT_ID_FORMAT, "COMPONENT PLDM FORMAT" }, \
526+
{ CXL_DER_VALID_SUB_CHANNEL, "SUB CHANNEL" } \
515527
)
516528

517529
TRACE_EVENT(cxl_dram,
@@ -540,6 +552,12 @@ TRACE_EVENT(cxl_dram,
540552
__field(u8, bank_group) /* Out of order to pack trace record */
541553
__field(u8, bank) /* Out of order to pack trace record */
542554
__field(u8, dpa_flags) /* Out of order to pack trace record */
555+
/* Following are out of order to pack trace record */
556+
__array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE)
557+
__field(u32, cvme_count)
558+
__field(u8, sub_type)
559+
__field(u8, sub_channel)
560+
__field(u8, cme_threshold_ev_flags)
543561
__string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
544562
),
545563

@@ -553,6 +571,7 @@ TRACE_EVENT(cxl_dram,
553571
__entry->dpa &= CXL_DPA_MASK;
554572
__entry->descriptor = rec->media_hdr.descriptor;
555573
__entry->type = rec->media_hdr.type;
574+
__entry->sub_type = rec->sub_type;
556575
__entry->transaction_type = rec->media_hdr.transaction_type;
557576
__entry->validity_flags = get_unaligned_le16(rec->media_hdr.validity_flags);
558577
__entry->channel = rec->media_hdr.channel;
@@ -572,23 +591,40 @@ TRACE_EVENT(cxl_dram,
572591
__assign_str(region_name);
573592
uuid_copy(&__entry->region_uuid, &uuid_null);
574593
}
594+
memcpy(__entry->comp_id, &rec->component_id,
595+
CXL_EVENT_GEN_MED_COMP_ID_SIZE);
596+
__entry->sub_channel = rec->sub_channel;
597+
__entry->cme_threshold_ev_flags = rec->cme_threshold_ev_flags;
598+
__entry->cvme_count = get_unaligned_le24(rec->cvme_count);
575599
),
576600

577-
CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' descriptor='%s' type='%s' " \
601+
CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' descriptor='%s' type='%s' sub_type='%s' " \
578602
"transaction_type='%s' channel=%u rank=%u nibble_mask=%x " \
579603
"bank_group=%u bank=%u row=%u column=%u cor_mask=%s " \
580604
"validity_flags='%s' " \
581-
"hpa=%llx region=%s region_uuid=%pUb",
605+
"comp_id=%s comp_id_pldm_valid_flags='%s' " \
606+
"pldm_entity_id=%s pldm_resource_id=%s " \
607+
"hpa=%llx region=%s region_uuid=%pUb " \
608+
"sub_channel=%u cme_threshold_ev_flags='%s' cvme_count=%u",
582609
__entry->dpa, show_dpa_flags(__entry->dpa_flags),
583610
show_event_desc_flags(__entry->descriptor),
584611
show_dram_mem_event_type(__entry->type),
612+
show_mem_event_sub_type(__entry->sub_type),
585613
show_trans_type(__entry->transaction_type),
586614
__entry->channel, __entry->rank, __entry->nibble_mask,
587615
__entry->bank_group, __entry->bank,
588616
__entry->row, __entry->column,
589617
__print_hex(__entry->cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE),
590618
show_dram_valid_flags(__entry->validity_flags),
591-
__entry->hpa, __get_str(region_name), &__entry->region_uuid
619+
__print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE),
620+
show_comp_id_pldm_flags(__entry->comp_id[0]),
621+
show_pldm_entity_id(__entry->validity_flags, CXL_DER_VALID_COMPONENT,
622+
CXL_DER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id),
623+
show_pldm_resource_id(__entry->validity_flags, CXL_DER_VALID_COMPONENT,
624+
CXL_DER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id),
625+
__entry->hpa, __get_str(region_name), &__entry->region_uuid,
626+
__entry->sub_channel, show_cme_threshold_ev_flags(__entry->cme_threshold_ev_flags),
627+
__entry->cvme_count
592628
)
593629
);
594630

‎include/cxl/event.h

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ struct cxl_event_gen_media {
6060

6161
/*
6262
* DRAM Event Record - DER
63-
* CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44
63+
* CXL rev 3.1 section 8.2.9.2.1.2; Table 8-46
6464
*/
6565
#define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20
6666
struct cxl_event_dram {
@@ -71,7 +71,12 @@ struct cxl_event_dram {
7171
u8 row[3];
7272
u8 column[2];
7373
u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE];
74-
u8 reserved[0x17];
74+
u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
75+
u8 sub_channel;
76+
u8 cme_threshold_ev_flags;
77+
u8 cvme_count[3];
78+
u8 sub_type;
79+
u8 reserved;
7580
} __packed;
7681

7782
/*

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