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cxl/hdm: Extend DVSEC range register emulation for region enumeration
One motivation for mapping range registers to decoder objects is to use those settings for region autodiscovery. The need to map a region for devices programmed to use range registers is especially urgent now that the kernel no longer routes "Soft Reserved" ranges in the memory map to device-dax by default. The CXL memory range loses all access mechanisms. Complete the implementation by marking the DPA reservation and setting the endpoint-decoder state to signal autodiscovery. Note that the default settings of ways=1 and granularity=4096 set in cxl_decode_init() do not need to be updated. Fixes: 09d09e0 ("cxl/dax: Create dax devices for CXL RAM regions") Tested-by: Dave Jiang <dave.jiang@intel.com> Tested-by: Gregory Price <gregory.price@memverge.com> Link: https://lore.kernel.org/r/168012575521.221280.14177293493678527326.stgit@dwillia2-xfh.jf.intel.com Reviewed-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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drivers/cxl/core/hdm.c

Lines changed: 22 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -738,14 +738,20 @@ static int cxl_decoder_reset(struct cxl_decoder *cxld)
738738
return 0;
739739
}
740740

741-
static int cxl_setup_hdm_decoder_from_dvsec(struct cxl_port *port,
742-
struct cxl_decoder *cxld, int which,
743-
struct cxl_endpoint_dvsec_info *info)
741+
static int cxl_setup_hdm_decoder_from_dvsec(
742+
struct cxl_port *port, struct cxl_decoder *cxld, u64 *dpa_base,
743+
int which, struct cxl_endpoint_dvsec_info *info)
744744
{
745+
struct cxl_endpoint_decoder *cxled;
746+
u64 len;
747+
int rc;
748+
745749
if (!is_cxl_endpoint(port))
746750
return -EOPNOTSUPP;
747751

748-
if (!range_len(&info->dvsec_range[which]))
752+
cxled = to_cxl_endpoint_decoder(&cxld->dev);
753+
len = range_len(&info->dvsec_range[which]);
754+
if (!len)
749755
return -ENOENT;
750756

751757
cxld->target_type = CXL_DECODER_EXPANDER;
@@ -760,6 +766,16 @@ static int cxl_setup_hdm_decoder_from_dvsec(struct cxl_port *port,
760766
cxld->flags |= CXL_DECODER_F_ENABLE | CXL_DECODER_F_LOCK;
761767
port->commit_end = cxld->id;
762768

769+
rc = devm_cxl_dpa_reserve(cxled, *dpa_base, len, 0);
770+
if (rc) {
771+
dev_err(&port->dev,
772+
"decoder%d.%d: Failed to reserve DPA range %#llx - %#llx\n (%d)",
773+
port->id, cxld->id, *dpa_base, *dpa_base + len - 1, rc);
774+
return rc;
775+
}
776+
*dpa_base += len;
777+
cxled->state = CXL_DECODER_STATE_AUTO;
778+
763779
return 0;
764780
}
765781

@@ -779,7 +795,8 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
779795
} target_list;
780796

781797
if (should_emulate_decoders(info))
782-
return cxl_setup_hdm_decoder_from_dvsec(port, cxld, which, info);
798+
return cxl_setup_hdm_decoder_from_dvsec(port, cxld, dpa_base,
799+
which, info);
783800

784801
ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which));
785802
base = ioread64_hi_lo(hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(which));

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