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pbrkr
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pinctrl: renesas: rzg2l: Support output enable on RZ/G2L
On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK signal is selectable to support an Ethernet PHY operating in either MII or RGMII mode. By default, the signal is configured as an input and MII mode is supported. The ETH_MODE register can be modified to configure this signal as an output to support RGMII mode. As this signal is by default an input, and can optionally be switched to an output, it maps neatly onto an `output-enable` property in the device tree. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240625200316.4282-4-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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‎drivers/pinctrl/renesas/pinctrl-rzg2l.c

Lines changed: 63 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -999,6 +999,60 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
999999
return false;
10001000
}
10011001

1002+
static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1003+
{
1004+
u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
1005+
u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data);
1006+
u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);
1007+
1008+
if (pin > pctrl->data->hwcfg->oen_max_pin)
1009+
return -EINVAL;
1010+
1011+
/*
1012+
* We can determine which Ethernet interface we're dealing with from
1013+
* the caps.
1014+
*/
1015+
if (caps & PIN_CFG_IO_VMC_ETH0)
1016+
return 0;
1017+
if (caps & PIN_CFG_IO_VMC_ETH1)
1018+
return 1;
1019+
1020+
return -EINVAL;
1021+
}
1022+
1023+
static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1024+
{
1025+
int bit;
1026+
1027+
bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1028+
if (bit < 0)
1029+
return 0;
1030+
1031+
return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
1032+
}
1033+
1034+
static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1035+
{
1036+
unsigned long flags;
1037+
int bit;
1038+
u8 val;
1039+
1040+
bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1041+
if (bit < 0)
1042+
return bit;
1043+
1044+
spin_lock_irqsave(&pctrl->lock, flags);
1045+
val = readb(pctrl->base + ETH_MODE);
1046+
if (oen)
1047+
val &= ~BIT(bit);
1048+
else
1049+
val |= BIT(bit);
1050+
writeb(val, pctrl->base + ETH_MODE);
1051+
spin_unlock_irqrestore(&pctrl->lock, flags);
1052+
1053+
return 0;
1054+
}
1055+
10021056
static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
10031057
{
10041058
u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
@@ -1775,7 +1829,7 @@ static const u64 r9a07g044_gpio_configs[] = {
17751829
RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
17761830
RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
17771831
RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
1778-
RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1832+
RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
17791833
RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
17801834
RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
17811835
RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
@@ -1784,7 +1838,7 @@ static const u64 r9a07g044_gpio_configs[] = {
17841838
RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
17851839
RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
17861840
RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1787-
RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1841+
RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
17881842
RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
17891843
RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
17901844
RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
@@ -1808,13 +1862,13 @@ static const u64 r9a07g044_gpio_configs[] = {
18081862

18091863
static const u64 r9a07g043_gpio_configs[] = {
18101864
RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
1811-
RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1865+
RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
18121866
RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
18131867
RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
18141868
RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
18151869
RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
18161870
RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
1817-
RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1871+
RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
18181872
RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
18191873
RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
18201874
RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
@@ -3007,6 +3061,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
30073061
[RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,
30083062
},
30093063
.iolh_groupb_oi = { 100, 66, 50, 33, },
3064+
.oen_max_pin = 0,
30103065
};
30113066

30123067
static const struct rzg2l_hwcfg rzg3s_hwcfg = {
@@ -3061,6 +3116,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
30613116
#endif
30623117
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
30633118
.pmc_writeb = &rzg2l_pmc_writeb,
3119+
.oen_read = &rzg2l_read_oen,
3120+
.oen_write = &rzg2l_write_oen,
30643121
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
30653122
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
30663123
};
@@ -3076,6 +3133,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
30763133
.hwcfg = &rzg2l_hwcfg,
30773134
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
30783135
.pmc_writeb = &rzg2l_pmc_writeb,
3136+
.oen_read = &rzg2l_read_oen,
3137+
.oen_write = &rzg2l_write_oen,
30793138
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
30803139
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
30813140
};

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