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bebarinobebarino
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Merge tag 'renesas-clk-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add graphics clock support on RZ/G2M, RZ/G2N, RZ/G2E, and R-Car H3, M3-W, and M3-N SoCs - Add Clocked Serial Interface (CSI) clocks on RZ/V2M - Add PWM (MTU3) clock and reset on RZ/G2UL and RZ/Five - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a77965: Add 3DGE and ZG support clk: renesas: r8a7796: Add 3DGE and ZG support clk: renesas: r8a7795: Add 3DGE and ZG support clk: renesas: emev2: Remove obsolete clkdev registration clk: renesas: r9a07g043: Add MTU3a clock and reset entry clk: renesas: rzg2l: Simplify .determine_rate() clk: renesas: r9a09g011: Add CSI related clocks clk: renesas: r8a774b1: Add 3DGE and ZG support clk: renesas: r8a774e1: Add 3DGE and ZG support clk: renesas: r8a774a1: Add 3DGE and ZG support clk: renesas: rcar-gen3: Add support for ZG clock
2 parents 06c2afb + dec5779 commit 226ab01

12 files changed

+63
-14
lines changed

‎drivers/clk/renesas/clk-emev2.c

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@
66
* Copyright (C) 2012 Magnus Damm
77
*/
88
#include <linux/clk-provider.h>
9-
#include <linux/clkdev.h>
109
#include <linux/io.h>
1110
#include <linux/of.h>
1211
#include <linux/of_address.h>
@@ -74,7 +73,6 @@ static void __init emev2_smu_clkdiv_init(struct device_node *np)
7473
clk = clk_register_divider(NULL, np->name, parent_name, 0,
7574
smu_base + reg[0], reg[1], 8, 0, &lock);
7675
of_clk_add_provider(np, of_clk_src_simple_get, clk);
77-
clk_register_clkdev(clk, np->full_name, NULL);
7876
pr_debug("## %s %pOFn %p\n", __func__, np, clk);
7977
}
8078
CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
@@ -92,7 +90,6 @@ static void __init emev2_smu_gclk_init(struct device_node *np)
9290
clk = clk_register_gate(NULL, np->name, parent_name, 0,
9391
smu_base + reg[0], reg[1], 0, &lock);
9492
of_clk_add_provider(np, of_clk_src_simple_get, clk);
95-
clk_register_clkdev(clk, np->full_name, NULL);
9693
pr_debug("## %s %pOFn %p\n", __func__, np, clk);
9794
}
9895
CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);

‎drivers/clk/renesas/r8a774a1-cpg-mssr.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
7676
/* Core Clock Outputs */
7777
DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
7878
DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
79+
DEF_GEN3_Z("zg", R8A774A1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
7980
DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
8081
DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
8182
DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -123,6 +124,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
123124
};
124125

125126
static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
127+
DEF_MOD("3dge", 112, R8A774A1_CLK_ZG),
126128
DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6),
127129
DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2),
128130
DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2),

‎drivers/clk/renesas/r8a774b1-cpg-mssr.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
7373

7474
/* Core Clock Outputs */
7575
DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
76+
DEF_GEN3_Z("zg", R8A774B1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
7677
DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
7778
DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
7879
DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -120,6 +121,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
120121
};
121122

122123
static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
124+
DEF_MOD("3dge", 112, R8A774B1_CLK_ZG),
123125
DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
124126
DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
125127
DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),

‎drivers/clk/renesas/r8a774e1-cpg-mssr.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
7676
/* Core Clock Outputs */
7777
DEF_GEN3_Z("z", R8A774E1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
7878
DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
79+
DEF_GEN3_Z("zg", R8A774E1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
7980
DEF_FIXED("ztr", R8A774E1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
8081
DEF_FIXED("ztrd2", R8A774E1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
8182
DEF_FIXED("zt", R8A774E1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -124,6 +125,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
124125
};
125126

126127
static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
128+
DEF_MOD("3dge", 112, R8A774E1_CLK_ZG),
127129
DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
128130
DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
129131
DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6),

‎drivers/clk/renesas/r8a7795-cpg-mssr.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
7979
/* Core Clock Outputs */
8080
DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
8181
DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
82+
DEF_GEN3_Z("zg", R8A7795_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
8283
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
8384
DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
8485
DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -128,6 +129,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
128129
};
129130

130131
static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
132+
DEF_MOD("3dge", 112, R8A7795_CLK_ZG),
131133
DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
132134
DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
133135
DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6),

‎drivers/clk/renesas/r8a7796-cpg-mssr.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
8181
/* Core Clock Outputs */
8282
DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
8383
DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
84+
DEF_GEN3_Z("zg", R8A7796_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
8485
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
8586
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
8687
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -130,6 +131,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
130131
};
131132

132133
static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
134+
DEF_MOD("3dge", 112, R8A7796_CLK_ZG),
133135
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
134136
DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6),
135137
DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2),

‎drivers/clk/renesas/r8a77965-cpg-mssr.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
7676

7777
/* Core Clock Outputs */
7878
DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
79+
DEF_GEN3_Z("zg", R8A77965_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
7980
DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
8081
DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
8182
DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -125,6 +126,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
125126
};
126127

127128
static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
129+
DEF_MOD("3dge", 112, R8A77965_CLK_ZG),
128130
DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
129131
DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6),
130132
DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2),

‎drivers/clk/renesas/r9a07g043-cpg.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -154,6 +154,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
154154
0x534, 1),
155155
DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
156156
0x534, 2),
157+
DEF_MOD("mtu_x_mck", R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0,
158+
0x538, 0),
157159
DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0,
158160
0x548, 0),
159161
DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
@@ -264,6 +266,7 @@ static struct rzg2l_reset r9a07g043_resets[] = {
264266
DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
265267
DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
266268
DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
269+
DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0),
267270
DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
268271
DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
269272
DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),

‎drivers/clk/renesas/r9a09g011-cpg.c

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,8 @@
2828
#define DIV_W DDIV_PACK(0x328, 0, 3)
2929

3030
#define SEL_B SEL_PLL_PACK(0x214, 0, 1)
31+
#define SEL_CSI0 SEL_PLL_PACK(0x330, 0, 1)
32+
#define SEL_CSI4 SEL_PLL_PACK(0x330, 4, 1)
3133
#define SEL_D SEL_PLL_PACK(0x214, 1, 1)
3234
#define SEL_E SEL_PLL_PACK(0x214, 2, 1)
3335
#define SEL_SDI SEL_PLL_PACK(0x300, 0, 1)
@@ -58,6 +60,8 @@ enum clk_ids {
5860
CLK_DIV_W,
5961
CLK_SEL_B,
6062
CLK_SEL_B_D2,
63+
CLK_SEL_CSI0,
64+
CLK_SEL_CSI4,
6165
CLK_SEL_D,
6266
CLK_SEL_E,
6367
CLK_SEL_SDI,
@@ -108,6 +112,7 @@ static const struct clk_div_table dtable_divw[] = {
108112

109113
/* Mux clock tables */
110114
static const char * const sel_b[] = { ".main", ".divb" };
115+
static const char * const sel_csi[] = { ".main_24", ".main" };
111116
static const char * const sel_d[] = { ".main", ".divd" };
112117
static const char * const sel_e[] = { ".main", ".dive" };
113118
static const char * const sel_w[] = { ".main", ".divw" };
@@ -139,6 +144,8 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
139144
DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d),
140145
DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e),
141146
DEF_MUX(".selsdi", CLK_SEL_SDI, SEL_SDI, sel_sdi),
147+
DEF_MUX(".selcsi0", CLK_SEL_CSI0, SEL_CSI0, sel_csi),
148+
DEF_MUX(".selcsi4", CLK_SEL_CSI4, SEL_CSI4, sel_csi),
142149
DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w),
143150

144151
DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2),
@@ -196,8 +203,12 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
196203
DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8),
197204
DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9),
198205
DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10),
206+
DEF_MOD("cperi_grpg", R9A09G011_CPERI_GRPG_PCLK, CLK_SEL_E, 0x438, 0),
207+
DEF_MOD("cperi_grph", R9A09G011_CPERI_GRPH_PCLK, CLK_SEL_E, 0x438, 1),
199208
DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4),
200209
DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5),
210+
DEF_MOD("csi0_clk", R9A09G011_CSI0_CLK, CLK_SEL_CSI0, 0x438, 8),
211+
DEF_MOD("csi4_clk", R9A09G011_CSI4_CLK, CLK_SEL_CSI4, 0x438, 12),
201212
DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0),
202213
};
203214

@@ -215,6 +226,8 @@ static const struct rzg2l_reset r9a09g011_resets[] = {
215226
DEF_RST(R9A09G011_TIM_GPB_PRESETN, 0x614, 1),
216227
DEF_RST(R9A09G011_TIM_GPC_PRESETN, 0x614, 2),
217228
DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN, 0x614, 5, 23),
229+
DEF_RST_MON(R9A09G011_CSI_GPG_PRESETN, 0x614, 6, 22),
230+
DEF_RST_MON(R9A09G011_CSI_GPH_PRESETN, 0x614, 7, 23),
218231
DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8),
219232
DEF_RST(R9A09G011_IIC_GPB_PRESETN, 0x614, 9),
220233
DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19),
@@ -225,6 +238,8 @@ static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {
225238
MOD_CLK_BASE + R9A09G011_CPERI_GRPB_PCLK,
226239
MOD_CLK_BASE + R9A09G011_CPERI_GRPC_PCLK,
227240
MOD_CLK_BASE + R9A09G011_CPERI_GRPF_PCLK,
241+
MOD_CLK_BASE + R9A09G011_CPERI_GRPG_PCLK,
242+
MOD_CLK_BASE + R9A09G011_CPERI_GRPH_PCLK,
228243
MOD_CLK_BASE + R9A09G011_GIC_CLK,
229244
MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK,
230245
MOD_CLK_BASE + R9A09G011_URT_PCLK,

‎drivers/clk/renesas/rcar-gen3-cpg.c

Lines changed: 31 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -264,11 +264,13 @@ static const struct clk_ops cpg_z_clk_ops = {
264264
.set_rate = cpg_z_clk_set_rate,
265265
};
266266

267-
static struct clk * __init cpg_z_clk_register(const char *name,
267+
static struct clk * __init __cpg_z_clk_register(const char *name,
268268
const char *parent_name,
269269
void __iomem *reg,
270270
unsigned int div,
271-
unsigned int offset)
271+
unsigned int offset,
272+
unsigned int fcr,
273+
unsigned int flags)
272274
{
273275
struct clk_init_data init = {};
274276
struct cpg_z_clk *zclk;
@@ -280,11 +282,11 @@ static struct clk * __init cpg_z_clk_register(const char *name,
280282

281283
init.name = name;
282284
init.ops = &cpg_z_clk_ops;
283-
init.flags = CLK_SET_RATE_PARENT;
285+
init.flags = flags;
284286
init.parent_names = &parent_name;
285287
init.num_parents = 1;
286288

287-
zclk->reg = reg + CPG_FRQCRC;
289+
zclk->reg = reg + fcr;
288290
zclk->kick_reg = reg + CPG_FRQCRB;
289291
zclk->hw.init = &init;
290292
zclk->mask = GENMASK(offset + 4, offset);
@@ -301,6 +303,27 @@ static struct clk * __init cpg_z_clk_register(const char *name,
301303
return clk;
302304
}
303305

306+
static struct clk * __init cpg_z_clk_register(const char *name,
307+
const char *parent_name,
308+
void __iomem *reg,
309+
unsigned int div,
310+
unsigned int offset)
311+
{
312+
return __cpg_z_clk_register(name, parent_name, reg, div, offset,
313+
CPG_FRQCRC, CLK_SET_RATE_PARENT);
314+
}
315+
316+
static struct clk * __init cpg_zg_clk_register(const char *name,
317+
const char *parent_name,
318+
void __iomem *reg,
319+
unsigned int div,
320+
unsigned int offset)
321+
{
322+
return __cpg_z_clk_register(name, parent_name, reg, div, offset,
323+
CPG_FRQCRB, 0);
324+
325+
}
326+
304327
static const struct clk_div_table cpg_rpcsrc_div_table[] = {
305328
{ 2, 5 }, { 3, 6 }, { 0, 0 },
306329
};
@@ -438,6 +461,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
438461
return cpg_z_clk_register(core->name, __clk_get_name(parent),
439462
base, core->div, core->offset);
440463

464+
case CLK_TYPE_GEN3_ZG:
465+
return cpg_zg_clk_register(core->name, __clk_get_name(parent),
466+
base, core->div, core->offset);
467+
441468
case CLK_TYPE_GEN3_OSC:
442469
/*
443470
* Clock combining OSC EXTAL predivider and a fixed divider

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