Skip to content

Commit 22439cf

Browse files
michalsimekrobherring
authored andcommitted
dt-bindings: fpga: altera: Convert bridge bindings to yaml
Convert Altera's bridges to yaml with using fpga-bridge.yaml. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/07d646a6d82cc21b100e45ced7cae3ef05faa2cc.1704807147.git.michal.simek@amd.com Signed-off-by: Rob Herring <robh@kernel.org>
1 parent 36a7c96 commit 22439cf

File tree

6 files changed

+123
-69
lines changed

6 files changed

+123
-69
lines changed

Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt

Lines changed: 0 additions & 13 deletions
This file was deleted.

Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt

Lines changed: 0 additions & 20 deletions
This file was deleted.

Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt

Lines changed: 0 additions & 36 deletions
This file was deleted.
Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/fpga/altr,freeze-bridge-controller.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Altera Freeze Bridge Controller
8+
9+
description:
10+
The Altera Freeze Bridge Controller manages one or more freeze bridges.
11+
The controller can freeze/disable the bridges which prevents signal
12+
changes from passing through the bridge. The controller can also
13+
unfreeze/enable the bridges which allows traffic to pass through the bridge
14+
normally.
15+
16+
maintainers:
17+
- Xu Yilun <yilun.xu@intel.com>
18+
19+
allOf:
20+
- $ref: fpga-bridge.yaml#
21+
22+
properties:
23+
compatible:
24+
const: altr,freeze-bridge-controller
25+
26+
reg:
27+
maxItems: 1
28+
29+
required:
30+
- compatible
31+
- reg
32+
33+
unevaluatedProperties: false
34+
35+
examples:
36+
- |
37+
fpga-bridge@100000450 {
38+
compatible = "altr,freeze-bridge-controller";
39+
reg = <0x1000 0x10>;
40+
bridge-enable = <0>;
41+
};
Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/fpga/altr,socfpga-fpga2sdram-bridge.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Altera FPGA To SDRAM Bridge
8+
9+
maintainers:
10+
- Xu Yilun <yilun.xu@intel.com>
11+
12+
allOf:
13+
- $ref: fpga-bridge.yaml#
14+
15+
properties:
16+
compatible:
17+
const: altr,socfpga-fpga2sdram-bridge
18+
19+
reg:
20+
maxItems: 1
21+
22+
required:
23+
- compatible
24+
25+
unevaluatedProperties: false
26+
27+
examples:
28+
- |
29+
fpga-bridge@ffc25080 {
30+
compatible = "altr,socfpga-fpga2sdram-bridge";
31+
reg = <0xffc25080 0x4>;
32+
bridge-enable = <0>;
33+
};
Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,49 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Altera FPGA/HPS Bridge
8+
9+
maintainers:
10+
- Xu Yilun <yilun.xu@intel.com>
11+
12+
allOf:
13+
- $ref: fpga-bridge.yaml#
14+
15+
properties:
16+
compatible:
17+
enum:
18+
- altr,socfpga-lwhps2fpga-bridge
19+
- altr,socfpga-hps2fpga-bridge
20+
- altr,socfpga-fpga2hps-bridge
21+
22+
reg:
23+
maxItems: 1
24+
25+
resets:
26+
maxItems: 1
27+
28+
clocks:
29+
maxItems: 1
30+
31+
required:
32+
- compatible
33+
- reg
34+
- clocks
35+
- resets
36+
37+
unevaluatedProperties: false
38+
39+
examples:
40+
- |
41+
#include <dt-bindings/reset/altr,rst-mgr.h>
42+
43+
fpga-bridge@ff400000 {
44+
compatible = "altr,socfpga-lwhps2fpga-bridge";
45+
reg = <0xff400000 0x100000>;
46+
bridge-enable = <0>;
47+
clocks = <&l4_main_clk>;
48+
resets = <&rst LWHPS2FPGA_RESET>;
49+
};

0 commit comments

Comments
 (0)