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reset: starfive: Factor out common JH71X0 reset code
The StarFive JH7100 SoC has additional reset controllers for audio and video, but the registers follow the same structure. On the JH7110 the reset registers don't get their own memory range, but instead follow the clock control registers. The registers still follow the same structure though, so let's factor out the common code to handle all these cases. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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‎drivers/reset/starfive/Kconfig

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@@ -1,8 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config RESET_STARFIVE_JH71X0
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bool
5+
36
config RESET_STARFIVE_JH7100
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bool "StarFive JH7100 Reset Driver"
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depends on ARCH_STARFIVE || COMPILE_TEST
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select RESET_STARFIVE_JH71X0
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default ARCH_STARFIVE
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help
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This enables the reset controller driver for the StarFive JH7100 SoC.

‎drivers/reset/starfive/Makefile

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@@ -1,2 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
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24
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o

‎drivers/reset/starfive/reset-starfive-jh7100.c

Lines changed: 1 addition & 149 deletions
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@@ -5,158 +5,10 @@
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* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
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*/
77

8-
#include <linux/bitmap.h>
9-
#include <linux/io.h>
10-
#include <linux/io-64-nonatomic-lo-hi.h>
11-
#include <linux/iopoll.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
14-
#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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17-
#include <dt-bindings/reset/starfive-jh7100.h>
18-
19-
/* register offsets */
20-
#define JH7100_RESET_ASSERT0 0x00
21-
#define JH7100_RESET_ASSERT1 0x04
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#define JH7100_RESET_ASSERT2 0x08
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#define JH7100_RESET_ASSERT3 0x0c
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#define JH7100_RESET_STATUS0 0x10
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#define JH7100_RESET_STATUS1 0x14
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#define JH7100_RESET_STATUS2 0x18
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#define JH7100_RESET_STATUS3 0x1c
28-
29-
/*
30-
* Writing a 1 to the n'th bit of the m'th ASSERT register asserts
31-
* line 32m + n, and writing a 0 deasserts the same line.
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* Most reset lines have their status inverted so a 0 bit in the STATUS
33-
* register means the line is asserted and a 1 means it's deasserted. A few
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* lines don't though, so store the expected value of the status registers when
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* all lines are asserted.
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*/
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static const u64 jh7100_reset_asserted[2] = {
38-
/* STATUS0 */
39-
BIT_ULL_MASK(JH7100_RST_U74) |
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BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
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BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
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/* STATUS1 */
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BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
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BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
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/* STATUS2 */
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BIT_ULL_MASK(JH7100_RST_E24) |
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/* STATUS3 */
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0,
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};
50-
51-
struct jh7100_reset {
52-
struct reset_controller_dev rcdev;
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/* protect registers against concurrent read-modify-write */
54-
spinlock_t lock;
55-
void __iomem *base;
56-
};
57-
58-
static inline struct jh7100_reset *
59-
jh7100_reset_from(struct reset_controller_dev *rcdev)
60-
{
61-
return container_of(rcdev, struct jh7100_reset, rcdev);
62-
}
63-
64-
static int jh7100_reset_update(struct reset_controller_dev *rcdev,
65-
unsigned long id, bool assert)
66-
{
67-
struct jh7100_reset *data = jh7100_reset_from(rcdev);
68-
unsigned long offset = BIT_ULL_WORD(id);
69-
u64 mask = BIT_ULL_MASK(id);
70-
void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
71-
void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
72-
u64 done = jh7100_reset_asserted[offset] & mask;
73-
u64 value;
74-
unsigned long flags;
75-
int ret;
76-
77-
if (!assert)
78-
done ^= mask;
79-
80-
spin_lock_irqsave(&data->lock, flags);
81-
82-
value = readq(reg_assert);
83-
if (assert)
84-
value |= mask;
85-
else
86-
value &= ~mask;
87-
writeq(value, reg_assert);
88-
89-
/* if the associated clock is gated, deasserting might otherwise hang forever */
90-
ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
91-
92-
spin_unlock_irqrestore(&data->lock, flags);
93-
return ret;
94-
}
95-
96-
static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
97-
unsigned long id)
98-
{
99-
return jh7100_reset_update(rcdev, id, true);
100-
}
101-
102-
static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
103-
unsigned long id)
104-
{
105-
return jh7100_reset_update(rcdev, id, false);
106-
}
107-
108-
static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
109-
unsigned long id)
110-
{
111-
int ret;
112-
113-
ret = jh7100_reset_assert(rcdev, id);
114-
if (ret)
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return ret;
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return jh7100_reset_deassert(rcdev, id);
118-
}
119-
120-
static int jh7100_reset_status(struct reset_controller_dev *rcdev,
121-
unsigned long id)
122-
{
123-
struct jh7100_reset *data = jh7100_reset_from(rcdev);
124-
unsigned long offset = BIT_ULL_WORD(id);
125-
u64 mask = BIT_ULL_MASK(id);
126-
void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
127-
u64 value = readq(reg_status);
128-
129-
return !((value ^ jh7100_reset_asserted[offset]) & mask);
130-
}
131-
132-
static const struct reset_control_ops jh7100_reset_ops = {
133-
.assert = jh7100_reset_assert,
134-
.deassert = jh7100_reset_deassert,
135-
.reset = jh7100_reset_reset,
136-
.status = jh7100_reset_status,
137-
};
138-
139-
static int __init jh7100_reset_probe(struct platform_device *pdev)
140-
{
141-
struct jh7100_reset *data;
142-
143-
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
144-
if (!data)
145-
return -ENOMEM;
146-
147-
data->base = devm_platform_ioremap_resource(pdev, 0);
148-
if (IS_ERR(data->base))
149-
return PTR_ERR(data->base);
150-
151-
data->rcdev.ops = &jh7100_reset_ops;
152-
data->rcdev.owner = THIS_MODULE;
153-
data->rcdev.nr_resets = JH7100_RSTN_END;
154-
data->rcdev.dev = &pdev->dev;
155-
data->rcdev.of_node = pdev->dev.of_node;
156-
spin_lock_init(&data->lock);
157-
158-
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
159-
}
11+
#include "reset-starfive-jh71x0.h"
16012

16113
static const struct of_device_id jh7100_reset_dt_ids[] = {
16214
{ .compatible = "starfive,jh7100-reset" },

‎drivers/reset/starfive/reset-starfive-jh71x0.c

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@@ -0,0 +1,162 @@
1+
// SPDX-License-Identifier: GPL-2.0-or-later
2+
/*
3+
* Reset driver for the StarFive JH7100 SoC
4+
*
5+
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
6+
*/
7+
8+
#include <linux/bitmap.h>
9+
#include <linux/device.h>
10+
#include <linux/io.h>
11+
#include <linux/io-64-nonatomic-lo-hi.h>
12+
#include <linux/iopoll.h>
13+
#include <linux/platform_device.h>
14+
#include <linux/reset-controller.h>
15+
#include <linux/spinlock.h>
16+
17+
#include "reset-starfive-jh71x0.h"
18+
19+
#include <dt-bindings/reset/starfive-jh7100.h>
20+
21+
/* register offsets */
22+
#define JH7100_RESET_ASSERT0 0x00
23+
#define JH7100_RESET_ASSERT1 0x04
24+
#define JH7100_RESET_ASSERT2 0x08
25+
#define JH7100_RESET_ASSERT3 0x0c
26+
#define JH7100_RESET_STATUS0 0x10
27+
#define JH7100_RESET_STATUS1 0x14
28+
#define JH7100_RESET_STATUS2 0x18
29+
#define JH7100_RESET_STATUS3 0x1c
30+
31+
/*
32+
* Writing a 1 to the n'th bit of the m'th ASSERT register asserts
33+
* line 32m + n, and writing a 0 deasserts the same line.
34+
* Most reset lines have their status inverted so a 0 bit in the STATUS
35+
* register means the line is asserted and a 1 means it's deasserted. A few
36+
* lines don't though, so store the expected value of the status registers when
37+
* all lines are asserted.
38+
*/
39+
static const u64 jh7100_reset_asserted[2] = {
40+
/* STATUS0 */
41+
BIT_ULL_MASK(JH7100_RST_U74) |
42+
BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
43+
BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
44+
/* STATUS1 */
45+
BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
46+
BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
47+
/* STATUS2 */
48+
BIT_ULL_MASK(JH7100_RST_E24) |
49+
/* STATUS3 */
50+
0,
51+
};
52+
53+
struct jh7100_reset {
54+
struct reset_controller_dev rcdev;
55+
/* protect registers against concurrent read-modify-write */
56+
spinlock_t lock;
57+
void __iomem *base;
58+
};
59+
60+
static inline struct jh7100_reset *
61+
jh7100_reset_from(struct reset_controller_dev *rcdev)
62+
{
63+
return container_of(rcdev, struct jh7100_reset, rcdev);
64+
}
65+
66+
static int jh7100_reset_update(struct reset_controller_dev *rcdev,
67+
unsigned long id, bool assert)
68+
{
69+
struct jh7100_reset *data = jh7100_reset_from(rcdev);
70+
unsigned long offset = BIT_ULL_WORD(id);
71+
u64 mask = BIT_ULL_MASK(id);
72+
void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
73+
void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
74+
u64 done = jh7100_reset_asserted[offset] & mask;
75+
u64 value;
76+
unsigned long flags;
77+
int ret;
78+
79+
if (!assert)
80+
done ^= mask;
81+
82+
spin_lock_irqsave(&data->lock, flags);
83+
84+
value = readq(reg_assert);
85+
if (assert)
86+
value |= mask;
87+
else
88+
value &= ~mask;
89+
writeq(value, reg_assert);
90+
91+
/* if the associated clock is gated, deasserting might otherwise hang forever */
92+
ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
93+
94+
spin_unlock_irqrestore(&data->lock, flags);
95+
return ret;
96+
}
97+
98+
static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
99+
unsigned long id)
100+
{
101+
return jh7100_reset_update(rcdev, id, true);
102+
}
103+
104+
static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
105+
unsigned long id)
106+
{
107+
return jh7100_reset_update(rcdev, id, false);
108+
}
109+
110+
static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
111+
unsigned long id)
112+
{
113+
int ret;
114+
115+
ret = jh7100_reset_assert(rcdev, id);
116+
if (ret)
117+
return ret;
118+
119+
return jh7100_reset_deassert(rcdev, id);
120+
}
121+
122+
static int jh7100_reset_status(struct reset_controller_dev *rcdev,
123+
unsigned long id)
124+
{
125+
struct jh7100_reset *data = jh7100_reset_from(rcdev);
126+
unsigned long offset = BIT_ULL_WORD(id);
127+
u64 mask = BIT_ULL_MASK(id);
128+
void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
129+
u64 value = readq(reg_status);
130+
131+
return !((value ^ jh7100_reset_asserted[offset]) & mask);
132+
}
133+
134+
static const struct reset_control_ops jh7100_reset_ops = {
135+
.assert = jh7100_reset_assert,
136+
.deassert = jh7100_reset_deassert,
137+
.reset = jh7100_reset_reset,
138+
.status = jh7100_reset_status,
139+
};
140+
141+
int jh7100_reset_probe(struct platform_device *pdev)
142+
{
143+
struct jh7100_reset *data;
144+
145+
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
146+
if (!data)
147+
return -ENOMEM;
148+
149+
data->base = devm_platform_ioremap_resource(pdev, 0);
150+
if (IS_ERR(data->base))
151+
return PTR_ERR(data->base);
152+
153+
data->rcdev.ops = &jh7100_reset_ops;
154+
data->rcdev.owner = THIS_MODULE;
155+
data->rcdev.nr_resets = JH7100_RSTN_END;
156+
data->rcdev.dev = &pdev->dev;
157+
data->rcdev.of_node = pdev->dev.of_node;
158+
spin_lock_init(&data->lock);
159+
160+
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
161+
}
162+
EXPORT_SYMBOL_GPL(jh7100_reset_probe);

‎drivers/reset/starfive/reset-starfive-jh71x0.h

Lines changed: 11 additions & 0 deletions
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@@ -0,0 +1,11 @@
1+
/* SPDX-License-Identifier: GPL-2.0-or-later */
2+
/*
3+
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
4+
*/
5+
6+
#ifndef __RESET_STARFIVE_JH71X0_H
7+
#define __RESET_STARFIVE_JH71X0_H
8+
9+
int jh7100_reset_probe(struct platform_device *pdev);
10+
11+
#endif /* __RESET_STARFIVE_JH71X0_H */

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