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wensbebarino
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clk: mediatek: mt8183: Add back SSPM related clocks
This reverts commit 860690a. On the MT8183, the SSPM related clocks were removed claiming a lack of usage. This however causes some issues when the driver was converted to the new simple-probe mechanism. This mechanism allocates enough space for all the clocks defined in the clock driver, not the highest index in the DT binding. This leads to out-of-bound writes if their are holes in the DT binding or the driver (due to deprecated or unimplemented clocks). These errors can go unnoticed and cause memory corruption, leading to crashes in unrelated areas, or nothing at all. KASAN will detect them. Add the SSPM related clocks back to the MT8183 clock driver to fully implement the DT binding. The SSPM clocks are for the power management co-processor, and should never be turned off. They are marked as such. Fixes: 3f37ba7 ("clk: mediatek: mt8183: Convert all remaining clocks to common probe") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230719074251.1219089-1-wenst@chromium.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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drivers/clk/mediatek/clk-mt8183.c

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@@ -328,6 +328,14 @@ static const char * const atb_parents[] = {
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"syspll_d5"
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};
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static const char * const sspm_parents[] = {
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"clk26m",
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"univpll_d2_d4",
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"syspll_d2_d2",
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"univpll_d2_d2",
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"syspll_d3"
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};
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static const char * const dpi0_parents[] = {
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"clk26m",
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"tvdpll_d2",
@@ -507,6 +515,9 @@ static const struct mtk_mux top_muxes[] = {
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/* CLK_CFG_6 */
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
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atb_parents, 0xa0, 0xa4, 0xa8, 0, 2, 7, 0x004, 24),
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MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SSPM, "sspm_sel",
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sspm_parents, 0xa0, 0xa4, 0xa8, 8, 3, 15, 0x004, 25,
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CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel",
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dpi0_parents, 0xa0, 0xa4, 0xa8, 16, 4, 23, 0x004, 26),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel",
@@ -673,10 +684,18 @@ static const struct mtk_gate_regs infra3_cg_regs = {
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GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr)
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#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flag) \
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GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, \
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_shift, &mtk_clk_gate_ops_setclr, _flag)
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#define GATE_INFRA3(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr)
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#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \
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GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, \
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_shift, &mtk_clk_gate_ops_setclr, _flag)
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static const struct mtk_gate infra_clks[] = {
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/* INFRA0 */
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GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "axi_sel", 0),
@@ -748,7 +767,11 @@ static const struct mtk_gate infra_clks[] = {
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GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "fufs_sel", 12),
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GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", "fufs_sel", 13),
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GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", "axi_sel", 14),
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/* infra_sspm is main clock in co-processor, should not be closed in Linux. */
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GATE_INFRA2_FLAGS(CLK_INFRA_SSPM, "infra_sspm", "sspm_sel", 15, CLK_IS_CRITICAL),
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GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16),
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/* infra_sspm_bus_hclk is main clock in co-processor, should not be closed in Linux. */
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GATE_INFRA2_FLAGS(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk", "axi_sel", 17, CLK_IS_CRITICAL),
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GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18),
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GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19),
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GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20),
@@ -766,6 +789,10 @@ static const struct mtk_gate infra_clks[] = {
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GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0),
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GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1),
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GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2),
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/* infra_sspm_26m_self is main clock in co-processor, should not be closed in Linux. */
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GATE_INFRA3_FLAGS(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self", "f_f26m_ck", 3, CLK_IS_CRITICAL),
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/* infra_sspm_32k_self is main clock in co-processor, should not be closed in Linux. */
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GATE_INFRA3_FLAGS(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self", "f_f26m_ck", 4, CLK_IS_CRITICAL),
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GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5),
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GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6),
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GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_hclk_sel", 7),

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