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drm/etnaviv: Expose a few more chipspecs to userspace
These ones will be needed to make use fo the NN and TP units in the NPUs based on Vivante IP. Also fix the number of NN cores in the VIPNano-qi. Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Acked-by: Christian Gmeiner <cgmeiner@igalia.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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‎drivers/gpu/drm/etnaviv/etnaviv_gpu.c

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -164,6 +164,26 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
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*value = gpu->identity.eco_id;
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break;
166166

167+
case ETNAVIV_PARAM_GPU_NN_CORE_COUNT:
168+
*value = gpu->identity.nn_core_count;
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break;
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171+
case ETNAVIV_PARAM_GPU_NN_MAD_PER_CORE:
172+
*value = gpu->identity.nn_mad_per_core;
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break;
174+
175+
case ETNAVIV_PARAM_GPU_TP_CORE_COUNT:
176+
*value = gpu->identity.tp_core_count;
177+
break;
178+
179+
case ETNAVIV_PARAM_GPU_ON_CHIP_SRAM_SIZE:
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*value = gpu->identity.on_chip_sram_size;
181+
break;
182+
183+
case ETNAVIV_PARAM_GPU_AXI_SRAM_SIZE:
184+
*value = gpu->identity.axi_sram_size;
185+
break;
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default:
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DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
169189
return -EINVAL;

‎drivers/gpu/drm/etnaviv/etnaviv_gpu.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,18 @@ struct etnaviv_chip_identity {
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/* Number of Neural Network cores. */
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u32 nn_core_count;
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57+
/* Number of MAD units per Neural Network core. */
58+
u32 nn_mad_per_core;
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60+
/* Number of Tensor Processing cores. */
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u32 tp_core_count;
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63+
/* Size in bytes of the SRAM inside the NPU. */
64+
u32 on_chip_sram_size;
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66+
/* Size in bytes of the SRAM across the AXI bus. */
67+
u32 axi_sram_size;
68+
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/* Size of the vertex cache. */
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u32 vertex_cache_size;
5971

‎drivers/gpu/drm/etnaviv/etnaviv_hwdb.c

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,10 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
1717
.thread_count = 128,
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.shader_core_count = 1,
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.nn_core_count = 0,
20+
.nn_mad_per_core = 0,
21+
.tp_core_count = 0,
22+
.on_chip_sram_size = 0,
23+
.axi_sram_size = 0,
2024
.vertex_cache_size = 8,
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.vertex_output_buffer_size = 1024,
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.pixel_pipes = 1,
@@ -48,6 +52,11 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
4852
.register_max = 64,
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.thread_count = 256,
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.shader_core_count = 1,
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.nn_core_count = 0,
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.nn_mad_per_core = 0,
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.tp_core_count = 0,
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.on_chip_sram_size = 0,
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.axi_sram_size = 0,
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.vertex_cache_size = 8,
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.vertex_output_buffer_size = 512,
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.pixel_pipes = 1,
@@ -80,6 +89,10 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
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.thread_count = 512,
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.shader_core_count = 2,
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.nn_core_count = 0,
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.nn_mad_per_core = 0,
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.tp_core_count = 0,
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.on_chip_sram_size = 0,
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.axi_sram_size = 0,
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.vertex_cache_size = 16,
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.vertex_output_buffer_size = 1024,
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.pixel_pipes = 1,
@@ -112,6 +125,10 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
112125
.thread_count = 512,
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.shader_core_count = 2,
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.nn_core_count = 0,
128+
.nn_mad_per_core = 0,
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.tp_core_count = 0,
130+
.on_chip_sram_size = 0,
131+
.axi_sram_size = 0,
115132
.vertex_cache_size = 16,
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.vertex_output_buffer_size = 1024,
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.pixel_pipes = 1,
@@ -143,6 +160,11 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
143160
.register_max = 64,
144161
.thread_count = 512,
145162
.shader_core_count = 2,
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.nn_core_count = 0,
164+
.nn_mad_per_core = 0,
165+
.tp_core_count = 0,
166+
.on_chip_sram_size = 0,
167+
.axi_sram_size = 0,
146168
.vertex_cache_size = 16,
147169
.vertex_output_buffer_size = 1024,
148170
.pixel_pipes = 1,
@@ -175,6 +197,10 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
175197
.thread_count = 1024,
176198
.shader_core_count = 4,
177199
.nn_core_count = 0,
200+
.nn_mad_per_core = 0,
201+
.tp_core_count = 0,
202+
.on_chip_sram_size = 0,
203+
.axi_sram_size = 0,
178204
.vertex_cache_size = 16,
179205
.vertex_output_buffer_size = 1024,
180206
.pixel_pipes = 2,
@@ -207,6 +233,10 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
207233
.thread_count = 256,
208234
.shader_core_count = 1,
209235
.nn_core_count = 8,
236+
.nn_mad_per_core = 64,
237+
.tp_core_count = 4,
238+
.on_chip_sram_size = 524288,
239+
.axi_sram_size = 1048576,
210240
.vertex_cache_size = 16,
211241
.vertex_output_buffer_size = 1024,
212242
.pixel_pipes = 1,
@@ -239,6 +269,10 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
239269
.thread_count = 256,
240270
.shader_core_count = 1,
241271
.nn_core_count = 6,
272+
.nn_mad_per_core = 64,
273+
.tp_core_count = 3,
274+
.on_chip_sram_size = 262144,
275+
.axi_sram_size = 0,
242276
.vertex_cache_size = 16,
243277
.vertex_output_buffer_size = 1024,
244278
.pixel_pipes = 1,

‎include/uapi/drm/etnaviv_drm.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,11 @@ struct drm_etnaviv_timespec {
7777
#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
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#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
7979
#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
80+
#define ETNAVIV_PARAM_GPU_NN_CORE_COUNT 0x1f
81+
#define ETNAVIV_PARAM_GPU_NN_MAD_PER_CORE 0x20
82+
#define ETNAVIV_PARAM_GPU_TP_CORE_COUNT 0x21
83+
#define ETNAVIV_PARAM_GPU_ON_CHIP_SRAM_SIZE 0x22
84+
#define ETNAVIV_PARAM_GPU_AXI_SRAM_SIZE 0x23
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8186
#define ETNA_MAX_PIPES 4
8287

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