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83 | 83 | clock-frequency = <24000000>;
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84 | 84 | };
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85 | 85 |
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| 86 | + display_subsystem { |
| 87 | + compatible = "rockchip,display-subsystem"; |
| 88 | + ports = <&vop_out>; |
| 89 | + }; |
| 90 | + |
86 | 91 | xin24m: oscillator {
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87 | 92 | compatible = "fixed-clock";
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88 | 93 | clock-frequency = <24000000>;
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371 | 376 | clock-names = "pclk", "timer";
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372 | 377 | };
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373 | 378 |
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| 379 | + vop: vop@ffb00000 { |
| 380 | + compatible = "rockchip,rv1126-vop"; |
| 381 | + reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; |
| 382 | + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| 383 | + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; |
| 384 | + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; |
| 385 | + reset-names = "axi", "ahb", "dclk"; |
| 386 | + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; |
| 387 | + iommus = <&vop_mmu>; |
| 388 | + power-domains = <&power RV1126_PD_VO>; |
| 389 | + status = "disabled"; |
| 390 | + |
| 391 | + vop_out: port { |
| 392 | + #address-cells = <1>; |
| 393 | + #size-cells = <0>; |
| 394 | + |
| 395 | + vop_out_rgb: endpoint@0 { |
| 396 | + reg = <0>; |
| 397 | + }; |
| 398 | + |
| 399 | + vop_out_dsi: endpoint@1 { |
| 400 | + reg = <1>; |
| 401 | + }; |
| 402 | + }; |
| 403 | + }; |
| 404 | + |
| 405 | + vop_mmu: iommu@ffb00f00 { |
| 406 | + compatible = "rockchip,iommu"; |
| 407 | + reg = <0xffb00f00 0x100>; |
| 408 | + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| 409 | + clock-names = "aclk", "iface"; |
| 410 | + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; |
| 411 | + #iommu-cells = <0>; |
| 412 | + power-domains = <&power RV1126_PD_VO>; |
| 413 | + status = "disabled"; |
| 414 | + }; |
| 415 | + |
374 | 416 | gmac: ethernet@ffc40000 {
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375 | 417 | compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
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376 | 418 | reg = <0xffc40000 0x4000>;
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