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victorlu-amdalexdeucher
victorlu-amd
authored and
alexdeucher
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drm/amdgpu: Change WREG32_RLC to WREG32_SOC15_RLC where inst != 0 (v2)
W/RREG32_RLC is hardedcoded to use instance 0. W/RREG32_SOC15_RLC should be used instead when inst != 0. v2: rebase Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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3 files changed

+37
-43
lines changed

3 files changed

+37
-43
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

Lines changed: 17 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -306,8 +306,7 @@ static int kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device *adev, void *mqd,
306306
/* Activate doorbell logic before triggering WPTR poll. */
307307
data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
308308
CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
309-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL),
310-
data);
309+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data);
311310

312311
if (wptr) {
313312
/* Don't read wptr with get_user because the user
@@ -336,27 +335,24 @@ static int kgd_gfx_v9_4_3_hqd_load(struct amdgpu_device *adev, void *mqd,
336335
guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
337336
guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
338337

339-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO),
340-
lower_32_bits(guessed_wptr));
341-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI),
342-
upper_32_bits(guessed_wptr));
343-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR),
344-
lower_32_bits((uintptr_t)wptr));
345-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
346-
regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
338+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO,
339+
lower_32_bits(guessed_wptr));
340+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI,
341+
upper_32_bits(guessed_wptr));
342+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR,
343+
lower_32_bits((uintptr_t)wptr));
344+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
347345
upper_32_bits((uintptr_t)wptr));
348-
WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1),
349-
(uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id,
350-
queue_id));
346+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1,
347+
(uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id));
351348
}
352349

353350
/* Start the EOP fetcher */
354-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR),
355-
REG_SET_FIELD(m->cp_hqd_eop_rptr,
356-
CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
351+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR,
352+
REG_SET_FIELD(m->cp_hqd_eop_rptr, CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
357353

358354
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
359-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE), data);
355+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data);
360356

361357
kgd_gfx_v9_release_queue(adev, inst);
362358

@@ -494,15 +490,15 @@ static uint32_t kgd_gfx_v9_4_3_set_address_watch(
494490
VALID,
495491
1);
496492

497-
WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
493+
WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
498494
regTCP_WATCH0_ADDR_H) +
499495
(watch_id * TCP_WATCH_STRIDE)),
500-
watch_address_high);
496+
watch_address_high, inst);
501497

502-
WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
498+
WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
503499
regTCP_WATCH0_ADDR_L) +
504500
(watch_id * TCP_WATCH_STRIDE)),
505-
watch_address_low);
501+
watch_address_low, inst);
506502

507503
return watch_address_cntl;
508504
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

Lines changed: 19 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -91,8 +91,8 @@ void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmi
9191
{
9292
kgd_gfx_v9_lock_srbm(adev, 0, 0, 0, vmid, inst);
9393

94-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG), sh_mem_config);
95-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_BASES), sh_mem_bases);
94+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config);
95+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases);
9696
/* APE1 no longer exists on GFX9 */
9797

9898
kgd_gfx_v9_unlock_srbm(adev, inst);
@@ -245,8 +245,7 @@ int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd,
245245
/* Activate doorbell logic before triggering WPTR poll. */
246246
data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
247247
CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
248-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL),
249-
data);
248+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data);
250249

251250
if (wptr) {
252251
/* Don't read wptr with get_user because the user
@@ -275,25 +274,24 @@ int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd,
275274
guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
276275
guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
277276

278-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO),
279-
lower_32_bits(guessed_wptr));
280-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI),
281-
upper_32_bits(guessed_wptr));
282-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR),
283-
lower_32_bits((uintptr_t)wptr));
284-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
285-
upper_32_bits((uintptr_t)wptr));
286-
WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1,
287-
(uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id));
277+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO,
278+
lower_32_bits(guessed_wptr));
279+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI,
280+
upper_32_bits(guessed_wptr));
281+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR,
282+
lower_32_bits((uintptr_t)wptr));
283+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
284+
upper_32_bits((uintptr_t)wptr));
285+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1,
286+
(uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id));
288287
}
289288

290289
/* Start the EOP fetcher */
291-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR),
292-
REG_SET_FIELD(m->cp_hqd_eop_rptr,
293-
CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
290+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR,
291+
REG_SET_FIELD(m->cp_hqd_eop_rptr, CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
294292

295293
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
296-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE), data);
294+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data);
297295

298296
kgd_gfx_v9_release_queue(adev, inst);
299297

@@ -556,7 +554,7 @@ int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd,
556554
break;
557555
}
558556

559-
WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST), type);
557+
WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST, type);
560558

561559
end_jiffies = (utimeout * HZ / 1000) + jiffies;
562560
while (true) {
@@ -908,8 +906,8 @@ void kgd_gfx_v9_get_iq_wait_times(struct amdgpu_device *adev,
908906
uint32_t inst)
909907

910908
{
911-
*wait_times = RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
912-
mmCP_IQ_WAIT_TIME2));
909+
*wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst),
910+
mmCP_IQ_WAIT_TIME2);
913911
}
914912

915913
void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev,

‎drivers/gpu/drm/amd/amdgpu/soc15_common.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -140,7 +140,7 @@
140140

141141
/* for GC only */
142142
#define RREG32_RLC(reg) \
143-
__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
143+
__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP, 0)
144144

145145
#define WREG32_RLC_NO_KIQ(reg, value, hwip) \
146146
__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)

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