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Merge tag 'soc-drivers-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann: "The main change this time was the introduction of the drivers/genpd subsystem that gets split out from drivers/soc to keep common functionality together. The SCMI driver subsystem gets an update to version 3.2 of the specification. There are also updates to memory, reset and other firmware drivers. On the soc driver side, the updates are mostly cleanups across a number of Arm platforms. On driver for loongarch adds power management for DT based systems, another driver is for HiSilicon's Arm server chips with their HCCS system health interface. The remaining updates for the most part add support for additional hardware in existing drivers or contain minor cleanups. Most of these are for the Qualcomm Snapdragon platform" * tag 'soc-drivers-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (136 commits) bus: fsl-mc: Use common ranges functions soc: kunpeng_hccs: fix some sparse warnings about incorrect type soc: loongson2_pm: add power management support soc: dt-bindings: add loongson-2 pm soc: rockchip: grf: Fix SDMMC not working on RK3588 with bus-width > 1 genpd: rockchip: Add PD_VO entry for rv1126 bus: ti-sysc: Fix cast to enum warning soc: kunpeng_hccs: add MAILBOX dependency MAINTAINERS: remove OXNAS entry dt-bindings: interrupt-controller: arm,versatile-fpga-irq: mark oxnas compatible as deprecated irqchip: irq-versatile-fpga: remove obsolete oxnas compatible soc: qcom: aoss: Tidy up qmp_send() callers soc: qcom: aoss: Format string in qmp_send() soc: qcom: aoss: Move length requirements from caller soc: kunpeng_hccs: fix size_t format string soc: ti: k3-socinfo.c: Add JTAG ID for AM62PX dt-bindings: firmware: qcom: scm: Updating VMID list firmware: imx: scu-irq: support identifying SCU wakeup source from sysfs firmware: imx: scu-irq: enlarge the IMX_SC_IRQ_NUM_GROUP firmware: imx: scu-irq: add imx_scu_irq_get_status ...
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‎Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs

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What: /sys/devices/platform/HISI04Bx:00/chipX/all_linked
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What: /sys/devices/platform/HISI04Bx:00/chipX/linked_full_lane
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What: /sys/devices/platform/HISI04Bx:00/chipX/crc_err_cnt
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Date: November 2023
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KernelVersion: 6.6
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Contact: Huisong Li <lihuisong@huawei.org>
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Description:
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The /sys/devices/platform/HISI04Bx:00/chipX/ directory
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contains read-only attributes exposing some summarization
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information of all HCCS ports under a specified chip.
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The X in 'chipX' indicates the Xth chip on platform.
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There are following attributes in this directory:
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================= ==== =========================================
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all_linked: (RO) if all enabled ports on this chip are
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linked (bool).
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linked_full_lane: (RO) if all linked ports on this chip are full
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lane (bool).
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crc_err_cnt: (RO) total CRC err count for all ports on this
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chip.
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================= ==== =========================================
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What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/all_linked
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What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/linked_full_lane
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What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/crc_err_cnt
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Date: November 2023
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KernelVersion: 6.6
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Contact: Huisong Li <lihuisong@huawei.org>
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Description:
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The /sys/devices/platform/HISI04Bx:00/chipX/dieY/ directory
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contains read-only attributes exposing some summarization
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information of all HCCS ports under a specified die.
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The Y in 'dieY' indicates the hardware id of the die on chip who
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has chip id X.
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There are following attributes in this directory:
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================= ==== =========================================
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all_linked: (RO) if all enabled ports on this die are
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linked (bool).
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linked_full_lane: (RO) if all linked ports on this die are full
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lane (bool).
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crc_err_cnt: (RO) total CRC err count for all ports on this
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die.
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================= ==== =========================================
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What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/type
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What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mode
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What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/enable
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What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/cur_lane_num
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What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/link_fsm
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What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mask
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What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/crc_err_cnt
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Date: November 2023
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KernelVersion: 6.6
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Contact: Huisong Li <lihuisong@huawei.org>
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Description:
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The /sys/devices/platform/HISI04Bx/chipX/dieX/hccsN/ directory
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contains read-only attributes exposing information about
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a HCCS port. The N value in 'hccsN' indicates this port id.
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The X in 'chipX' indicates the ID of the chip to which the
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HCCS port belongs. For example, X ranges from to 'n - 1' if the
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chip number on platform is n.
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The Y in 'dieY' indicates the hardware id of the die to which
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the hccs port belongs.
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Note: type, lane_mode and enable are fixed attributes on running
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platform.
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The HCCS port have the following attributes:
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============= ==== =============================================
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type: (RO) port type (string), e.g. HCCS-v1 -> H32
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lane_mode: (RO) the lane mode of this port (string), e.g. x8
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enable: (RO) indicate if this port is enabled (bool).
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cur_lane_num: (RO) current lane number of this port.
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link_fsm: (RO) link finite state machine of this port.
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lane_mask: (RO) current lane mask of this port, every bit
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indicates a lane.
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crc_err_cnt: (RO) CRC err count on this port.
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============= ==== =============================================

‎Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml

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@@ -82,7 +82,7 @@ additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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clock-controller@af00000 {
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compatible = "qcom,sm8250-dispcc";
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reg = <0x0af00000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
106-
power-domains = <&rpmhpd SM8250_MMCX>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml

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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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clock-controller@abf0000 {
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compatible = "qcom,sm8350-videocc";
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reg = <0x0abf0000 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&sleep_clk>;
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power-domains = <&rpmhpd SM8350_MMCX>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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#clock-cells = <1>;
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#reset-cells = <1>;

‎Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml

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- |
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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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clock-controller@ade0000 {
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compatible = "qcom,sm8450-camcc";
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reg = <0xade0000 0x20000>;
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clocks = <&gcc GCC_CAMERA_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&sleep_clk>;
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power-domains = <&rpmhpd SM8450_MMCX>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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#clock-cells = <1>;
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#reset-cells = <1>;

‎Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml

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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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clock-controller@af00000 {
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compatible = "qcom,sm8450-dispcc";
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reg = <0x0af00000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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power-domains = <&rpmhpd SM8450_MMCX>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml

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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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videocc: clock-controller@aaf0000 {
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compatible = "qcom,sm8450-videocc";
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reg = <0x0aaf0000 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_VIDEO_AHB_CLK>;
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power-domains = <&rpmhpd SM8450_MMCX>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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#clock-cells = <1>;
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#reset-cells = <1>;

‎Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml

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#include <dt-bindings/clock/qcom,sm8550-gcc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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clock-controller@af00000 {
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compatible = "qcom,sm8550-dispcc";
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reg = <0x0af00000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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power-domains = <&rpmhpd SM8550_MMCX>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,videocc.yaml

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examples:
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
127+
#include <dt-bindings/power/qcom,rpmhpd.h>
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clock-controller@ab00000 {
129129
compatible = "qcom,sdm845-videocc";
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reg = <0x0ab00000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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power-domains = <&rpmhpd SM8250_MMCX>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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...

‎Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml

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#include <dt-bindings/clock/qcom,gcc-sm8250.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
5656
#include <dt-bindings/interconnect/qcom,sm8250.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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display-controller@ae01000 {
6060
compatible = "qcom,sm8250-dpu";
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd SM8250_MMCX>;
75+
power-domains = <&rpmhpd RPMHPD_MMCX>;
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interrupt-parent = <&mdss>;
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interrupts = <0>;

‎Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml

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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
7878
#include <dt-bindings/interconnect/qcom,sm8250.h>
79-
#include <dt-bindings/power/qcom-rpmpd.h>
79+
#include <dt-bindings/power/qcom,rpmhpd.h>
8080
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display-subsystem@ae00000 {
8282
compatible = "qcom,sm8250-mdss";
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121121
assigned-clock-rates = <19200000>;
122122
123123
operating-points-v2 = <&mdp_opp_table>;
124-
power-domains = <&rpmhpd SM8250_MMCX>;
124+
power-domains = <&rpmhpd RPMHPD_MMCX>;
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interrupt-parent = <&mdss>;
127127
interrupts = <0>;
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196196
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
199-
power-domains = <&rpmhpd SM8250_MMCX>;
199+
power-domains = <&rpmhpd RPMHPD_MMCX>;
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phys = <&dsi0_phy>;
202202
phy-names = "dsi";
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assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
289-
power-domains = <&rpmhpd SM8250_MMCX>;
289+
power-domains = <&rpmhpd RPMHPD_MMCX>;
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291291
phys = <&dsi1_phy>;
292292
phy-names = "dsi";

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