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Merge branch 'pci/dt-bindings'
- Convert mobiveil-pcie.txt to YAML and update 'interrupt-names' and 'reg-names' (Frank Li) - Add qcom DT SM8550 and SM8650 optional 'global' interrupt for link events (Neil Armstrong) - Add qcom DT 'compatible' strings for IPQ5424 PCIe controller (Manikanta Mylavarapu) * pci/dt-bindings: dt-bindings: PCI: qcom: Document the IPQ5424 PCIe controller dt-bindings: PCI: qcom,pcie-sm8550: Document 'global' interrupt dt-bindings: PCI: mobiveil: Convert mobiveil-pcie.txt to YAML
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‎Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt

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‎Documentation/devicetree/bindings/pci/mbvl,gpex40-pcie.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/mbvl,gpex40-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mobiveil AXI PCIe Host Bridge
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maintainers:
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- Frank Li <Frank Li@nxp.com>
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description:
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Mobiveil's GPEX 4.0 is a PCIe Gen4 host bridge IP. This configurable IP
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has up to 8 outbound and inbound windows for address translation.
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NXP Layerscape PCIe Gen4 controller (Deprecated) base on Mobiveil's GPEX 4.0.
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properties:
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compatible:
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enum:
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- fsl,lx2160a-pcie
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- mbvl,gpex40-pcie
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reg:
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items:
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- description: PCIe controller registers
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- description: Bridge config registers
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- description: GPIO registers to control slot power
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- description: MSI registers
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minItems: 2
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reg-names:
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items:
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- const: csr_axi_slave
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- const: config_axi_slave
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- const: gpio_slave
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- const: apb_csr
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minItems: 2
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apio-wins:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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number of requested APIO outbound windows
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1. Config window
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2. Memory window
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default: 2
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maximum: 256
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ppio-wins:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: number of requested PPIO inbound windows
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default: 1
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maximum: 256
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interrupt-controller: true
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"#interrupt-cells":
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const: 1
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interrupts:
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minItems: 1
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maxItems: 3
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interrupt-names:
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minItems: 1
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maxItems: 3
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dma-coherent: true
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msi-parent: true
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required:
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- compatible
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- reg
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- reg-names
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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- if:
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properties:
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compatible:
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enum:
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- fsl,lx2160a-pcie
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then:
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properties:
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reg:
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maxItems: 2
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reg-names:
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maxItems: 2
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interrupts:
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minItems: 3
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interrupt-names:
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items:
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- const: aer
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- const: pme
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- const: intr
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else:
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properties:
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dma-coherent: false
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msi-parent: false
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interrupts:
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maxItems: 1
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interrupt-names: false
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie@b0000000 {
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compatible = "mbvl,gpex40-pcie";
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reg = <0xb0000000 0x00010000>,
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<0xa0000000 0x00001000>,
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<0xff000000 0x00200000>,
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<0xb0010000 0x00001000>;
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reg-names = "csr_axi_slave",
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"config_axi_slave",
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"gpio_slave",
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"apb_csr";
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ranges = <0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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apio-wins = <2>;
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ppio-wins = <1>;
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bus-range = <0x00 0xff>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 0 &pci_express 0>,
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<0 0 0 1 &pci_express 1>,
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<0 0 0 2 &pci_express 2>,
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<0 0 0 3 &pci_express 3>;
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@3400000 {
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compatible = "fsl,lx2160a-pcie";
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reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
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0x80 0x00000000 0x0 0x00001000>; /* configuration space */
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reg-names = "csr_axi_slave", "config_axi_slave";
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ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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interrupt-names = "aer", "pme", "intr";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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apio-wins = <8>;
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ppio-wins = <8>;
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dma-coherent;
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bus-range = <0x00 0xff>;
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msi-parent = <&its>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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};
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};

‎Documentation/devicetree/bindings/pci/mobiveil-pcie.txt

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‎Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml

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interrupts:
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minItems: 8
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maxItems: 8
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maxItems: 9
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interrupt-names:
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minItems: 8
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items:
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- const: msi0
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- const: msi1
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- const: msi5
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- const: msi6
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- const: msi7
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- const: global
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resets:
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minItems: 1
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3",
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"msi4", "msi5", "msi6", "msi7";
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"msi4", "msi5", "msi6", "msi7", "global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

‎Documentation/devicetree/bindings/pci/qcom,pcie.yaml

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- qcom,pcie-qcs404
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- qcom,pcie-sdm845
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- qcom,pcie-sdx55
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- items:
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- enum:
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- qcom,pcie-ipq5424
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- const: qcom,pcie-ipq9574
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- items:
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- const: qcom,pcie-msm8998
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- const: qcom,pcie-msm8996

‎MAINTAINERS

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@@ -17901,7 +17901,7 @@ M: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
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M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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L: linux-pci@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
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F: Documentation/devicetree/bindings/pci/mbvl,gpex40-pcie.yaml
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F: drivers/pci/controller/mobiveil/pcie-mobiveil*
1790617906

1790717907
PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)
@@ -17925,7 +17925,6 @@ M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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L: linux-pci@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
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F: drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
1793017929

1793117930
PCI DRIVER FOR PLDA PCIE IP

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