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linuswlinusw
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Merge tag 'renesas-pinctrl-for-v6.11-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v6.11 (take three) - Support output enable on RZ/G2L. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 parents 30b7748 + 2453e85 commit 11eaac6

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‎drivers/pinctrl/renesas/pinctrl-rzg2l.c

Lines changed: 95 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -294,8 +294,8 @@ struct rzg2l_pinctrl_data {
294294
#endif
295295
void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
296296
void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
297-
u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin);
298-
int (*oen_write)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen);
297+
u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
298+
int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);
299299
int (*hw_to_bias_param)(unsigned int val);
300300
int (*bias_param_to_hw)(enum pin_config_param param);
301301
};
@@ -999,53 +999,100 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
999999
return false;
10001000
}
10011001

1002-
static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin)
1002+
static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
10031003
{
1004-
if (!(caps & PIN_CFG_OEN))
1005-
return false;
1004+
u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
1005+
u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data);
1006+
u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);
10061007

1007-
if (pin > max_pin)
1008-
return false;
1008+
if (pin > pctrl->data->hwcfg->oen_max_pin)
1009+
return -EINVAL;
10091010

1010-
return true;
1011+
/*
1012+
* We can determine which Ethernet interface we're dealing with from
1013+
* the caps.
1014+
*/
1015+
if (caps & PIN_CFG_IO_VMC_ETH0)
1016+
return 0;
1017+
if (caps & PIN_CFG_IO_VMC_ETH1)
1018+
return 1;
1019+
1020+
return -EINVAL;
10111021
}
10121022

1013-
static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port)
1023+
static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
10141024
{
1015-
if (pin)
1016-
pin *= 2;
1025+
int bit;
10171026

1018-
if (offset / RZG2L_PINS_PER_PORT == max_port)
1019-
pin += 1;
1027+
bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1028+
if (bit < 0)
1029+
return 0;
10201030

1021-
return pin;
1031+
return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
10221032
}
10231033

1024-
static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
1034+
static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
10251035
{
1026-
u8 max_port = pctrl->data->hwcfg->oen_max_port;
1027-
u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
1028-
u8 bit;
1036+
unsigned long flags;
1037+
int bit;
1038+
u8 val;
10291039

1030-
if (!rzg2l_oen_is_supported(caps, pin, max_pin))
1031-
return 0;
1040+
bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1041+
if (bit < 0)
1042+
return bit;
10321043

1033-
bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
1044+
spin_lock_irqsave(&pctrl->lock, flags);
1045+
val = readb(pctrl->base + ETH_MODE);
1046+
if (oen)
1047+
val &= ~BIT(bit);
1048+
else
1049+
val |= BIT(bit);
1050+
writeb(val, pctrl->base + ETH_MODE);
1051+
spin_unlock_irqrestore(&pctrl->lock, flags);
10341052

1035-
return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
1053+
return 0;
10361054
}
10371055

1038-
static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
1056+
static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
10391057
{
1040-
u8 max_port = pctrl->data->hwcfg->oen_max_port;
1041-
u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
1042-
unsigned long flags;
1043-
u8 val, bit;
1058+
u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
1059+
u8 port, pin, bit;
10441060

1045-
if (!rzg2l_oen_is_supported(caps, pin, max_pin))
1061+
if (*pin_data & RZG2L_SINGLE_PIN)
10461062
return -EINVAL;
10471063

1048-
bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
1064+
port = RZG2L_PIN_ID_TO_PORT(_pin);
1065+
pin = RZG2L_PIN_ID_TO_PIN(_pin);
1066+
if (pin > pctrl->data->hwcfg->oen_max_pin)
1067+
return -EINVAL;
1068+
1069+
bit = pin * 2;
1070+
if (port == pctrl->data->hwcfg->oen_max_port)
1071+
bit += 1;
1072+
1073+
return bit;
1074+
}
1075+
1076+
static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1077+
{
1078+
int bit;
1079+
1080+
bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1081+
if (bit < 0)
1082+
return bit;
1083+
1084+
return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
1085+
}
1086+
1087+
static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1088+
{
1089+
unsigned long flags;
1090+
int bit;
1091+
u8 val;
1092+
1093+
bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1094+
if (bit < 0)
1095+
return bit;
10491096

10501097
spin_lock_irqsave(&pctrl->lock, flags);
10511098
val = readb(pctrl->base + ETH_MODE);
@@ -1124,12 +1171,12 @@ static int rzv2h_bias_param_to_hw(enum pin_config_param param)
11241171
return -EINVAL;
11251172
}
11261173

1127-
static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset)
1174+
static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
11281175
{
11291176
static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
11301177
"XSPI0_RESET0N", "XSPI0_CS0N",
11311178
"XSPI0_CKN", "XSPI0_CKP" };
1132-
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1179+
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin];
11331180
unsigned int i;
11341181

11351182
for (i = 0; i < ARRAY_SIZE(pin_names); i++) {
@@ -1141,30 +1188,24 @@ static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset)
11411188
return 0;
11421189
}
11431190

1144-
static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
1191+
static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
11451192
{
11461193
u8 bit;
11471194

1148-
if (!(caps & PIN_CFG_OEN))
1149-
return 0;
1150-
1151-
bit = rzv2h_pin_to_oen_bit(pctrl, offset);
1195+
bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
11521196

11531197
return !(readb(pctrl->base + PFC_OEN) & BIT(bit));
11541198
}
11551199

1156-
static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
1200+
static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
11571201
{
11581202
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
11591203
const struct rzg2l_register_offsets *regs = &hwcfg->regs;
11601204
unsigned long flags;
11611205
u8 val, bit;
11621206
u8 pwpr;
11631207

1164-
if (!(caps & PIN_CFG_OEN))
1165-
return -EINVAL;
1166-
1167-
bit = rzv2h_pin_to_oen_bit(pctrl, offset);
1208+
bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
11681209
spin_lock_irqsave(&pctrl->lock, flags);
11691210
val = readb(pctrl->base + PFC_OEN);
11701211
if (oen)
@@ -1220,7 +1261,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
12201261
break;
12211262

12221263
case PIN_CONFIG_OUTPUT_ENABLE:
1223-
arg = pctrl->data->oen_read(pctrl, cfg, _pin, bit);
1264+
if (!pctrl->data->oen_read || !(cfg & PIN_CFG_OEN))
1265+
return -EOPNOTSUPP;
1266+
arg = pctrl->data->oen_read(pctrl, _pin);
12241267
if (!arg)
12251268
return -EINVAL;
12261269
break;
@@ -1359,7 +1402,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
13591402

13601403
case PIN_CONFIG_OUTPUT_ENABLE:
13611404
arg = pinconf_to_config_argument(_configs[i]);
1362-
ret = pctrl->data->oen_write(pctrl, cfg, _pin, bit, !!arg);
1405+
if (!pctrl->data->oen_write || !(cfg & PIN_CFG_OEN))
1406+
return -EOPNOTSUPP;
1407+
ret = pctrl->data->oen_write(pctrl, _pin, !!arg);
13631408
if (ret)
13641409
return ret;
13651410
break;
@@ -1784,7 +1829,7 @@ static const u64 r9a07g044_gpio_configs[] = {
17841829
RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
17851830
RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
17861831
RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
1787-
RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1832+
RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
17881833
RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
17891834
RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
17901835
RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
@@ -1793,7 +1838,7 @@ static const u64 r9a07g044_gpio_configs[] = {
17931838
RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
17941839
RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
17951840
RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1796-
RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1841+
RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
17971842
RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
17981843
RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
17991844
RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
@@ -1817,13 +1862,13 @@ static const u64 r9a07g044_gpio_configs[] = {
18171862

18181863
static const u64 r9a07g043_gpio_configs[] = {
18191864
RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
1820-
RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1865+
RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
18211866
RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
18221867
RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
18231868
RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
18241869
RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
18251870
RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
1826-
RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1871+
RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
18271872
RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
18281873
RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
18291874
RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
@@ -3016,6 +3061,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
30163061
[RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,
30173062
},
30183063
.iolh_groupb_oi = { 100, 66, 50, 33, },
3064+
.oen_max_pin = 0,
30193065
};
30203066

30213067
static const struct rzg2l_hwcfg rzg3s_hwcfg = {
@@ -3103,8 +3149,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
31033149
.hwcfg = &rzg3s_hwcfg,
31043150
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
31053151
.pmc_writeb = &rzg2l_pmc_writeb,
3106-
.oen_read = &rzg2l_read_oen,
3107-
.oen_write = &rzg2l_write_oen,
3152+
.oen_read = &rzg3s_oen_read,
3153+
.oen_write = &rzg3s_oen_write,
31083154
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
31093155
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
31103156
};

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